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Searched refs:DestRC (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp35 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
38 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
42 if (DestRC == &NVPTX::B1RegClass) { in copyPhysReg()
44 } else if (DestRC == &NVPTX::B16RegClass) { in copyPhysReg()
46 } else if (DestRC == &NVPTX::B32RegClass) { in copyPhysReg()
48 } else if (DestRC == &NVPTX::B64RegClass) { in copyPhysReg()
50 } else if (DestRC == &NVPTX::B128RegClass) { in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp367 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
372 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
375 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
578 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
588 if (DestRC != RC) { in ListScheduleBottomUp()
590 if (!DestRC && !NewDef) in ListScheduleBottomUp()
597 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
H A DScheduleDAGRRList.cpp1220 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1225 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1228 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1566 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1576 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1578 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1584 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp1243 const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg); in foldOperand() local
1244 if (!DestReg.isPhysical() && DestRC == &AMDGPU::AGPR_32RegClass) { in foldOperand()
1257 if (DestRC == &AMDGPU::SGPR_LO16RegClass) { in foldOperand()
1260 DestRC = &AMDGPU::SGPR_32RegClass; in foldOperand()
1266 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
1277 if (!DestRC->hasSuperClassEq(ResRC)) in foldOperand()
H A DSIFixSGPRCopies.cpp677 const TargetRegisterClass *DestRC = in run() local
679 Register NewDst = MRI->createVirtualRegister(DestRC); in run()
H A DSIInstrInfo.cpp8289 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
8290 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
8535 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
8536 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
8579 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitXnor() local
8597 Register NewDest = MRI.createVirtualRegister(DestRC); in splitScalar64BitXnor()