Searched refs:DestRC (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.cpp | 37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
44 if (DestRC == &NVPTX::Int1RegsRegClass) { in copyPhysReg()
46 } else if (DestRC == &NVPTX::Int16RegsRegClass) { in copyPhysReg()
48 } else if (DestRC == &NVPTX::Int32RegsRegClass) { in copyPhysReg()
51 } else if (DestRC == &NVPTX::Int64RegsRegClass) { in copyPhysReg()
54 } else if (DestRC == &NVPTX::Int128RegsRegClass) { in copyPhysReg()
56 } else if (DestRC == &NVPTX::Float32RegsRegClass) { in copyPhysReg()
59 } else if (DestRC == &NVPTX::Float64RegsRegClass) { in copyPhysReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGFast.cpp | 373 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
378 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
381 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
585 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
595 if (DestRC != RC) { in ListScheduleBottomUp()
597 if (!DestRC && !NewDef) in ListScheduleBottomUp()
604 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
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| H A D | ScheduleDAGRRList.cpp | 1220 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1225 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1228 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1566 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1576 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1578 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1584 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 662 const TargetRegisterClass *DestRC = in runOnMachineFunction() local
664 Register NewDst = MRI->createVirtualRegister(DestRC); in runOnMachineFunction()
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| H A D | SIFoldOperands.cpp | 849 const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg); in foldOperand() local
851 if (DestRC == &AMDGPU::AGPR_32RegClass && in foldOperand()
863 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
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| H A D | SIInstrInfo.cpp | 7798 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
7799 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
8044 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
8045 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
8088 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitXnor() local
8106 Register NewDest = MRI.createVirtualRegister(DestRC); in splitScalar64BitXnor()
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