Searched refs:DesiredReg (Results 1 – 3 of 3) sorted by relevance
1820 Register DesiredReg = MI.getOperand(3).getReg(); in ExpandCMP_SWAP() local1828 assert((UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg)) && in ExpandCMP_SWAP()1843 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg) in ExpandCMP_SWAP()1844 .addReg(DesiredReg, RegState::Kill); in ExpandCMP_SWAP()1865 .addReg(DesiredReg) in ExpandCMP_SWAP()1950 Register DesiredReg = MI.getOperand(3).getReg(); in ExpandCMP_SWAP_64() local1956 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); in ExpandCMP_SWAP_64()1957 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); in ExpandCMP_SWAP_64()
248 Register DesiredReg = MI.getOperand(3).getReg(); in expandCMP_SWAP() local272 .addReg(DesiredReg) in expandCMP_SWAP()
5075 const Register DesiredReg = constrainOperandRegClass( in selectAtomicCmpXchg() local5089 .addUse(DesiredReg) in selectAtomicCmpXchg()5095 .addUse(DesiredReg) in selectAtomicCmpXchg()