Searched refs:DepCtr (Results 1 – 10 of 10) sorted by relevance
56 namespace DepCtr {
68 namespace DepCtr { namespace
1108 namespace DepCtr {
1635 namespace DepCtr { namespace
1180 AMDGPU::DepCtr::decodeFieldVmVsrc(MI.getOperand(0).getImm()) == 0); in fixVMEMtoScalarWriteHazards()1190 .addImm(AMDGPU::DepCtr::encodeFieldVmVsrc(0)); in fixVMEMtoScalarWriteHazards()1309 AMDGPU::DepCtr::decodeFieldSaSdst(MI.getOperand(0).getImm()) == 0) in fixVcmpxExecWARHazard()1320 .addImm(AMDGPU::DepCtr::encodeFieldSaSdst(0)); in fixVcmpxExecWARHazard()1472 AMDGPU::DepCtr::decodeFieldVmVsrc(I.getOperand(0).getImm()) == 0) || in fixLdsDirectVMEMHazard()1486 .addImm(AMDGPU::DepCtr::encodeFieldVmVsrc(0)); in fixLdsDirectVMEMHazard()1549 AMDGPU::DepCtr::decodeFieldVaVdst(I.getOperand(0).getImm()) == 0)) in fixVALUPartialForwardingHazard()1716 .addImm(AMDGPU::DepCtr::encodeFieldVaVdst(0)); in fixVALUTransUseHazard()2833 AMDGPU::DepCtr::decodeFieldSaSdst(I.getOperand(0).getImm()) == 0) in fixVALUMaskWriteHazard()2883 .addImm(AMDGPU::DepCtr::encodeFieldSaSdst(0)); in fixVALUMaskWriteHazard()
54 AMDGPU::DepCtr::decodeFieldVaVdst(MI.getOperand(0).getImm()) == 0) in instructionWaitsForVALU()
1724 SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtr:$simm16), "$simm16">;
936 def DepCtr : CustomOperand<i32>;
7281 bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) { in parseDepCtr() argument7283 using namespace llvm::AMDGPU::DepCtr; in parseDepCtr()7315 DepCtr = (DepCtr & ~CntValMask) | CntVal; in parseDepCtr()7320 using namespace llvm::AMDGPU::DepCtr; in parseDepCtr()7322 int64_t DepCtr = getDefaultDepCtrEncoding(getSTI()); in parseDepCtr() local7328 if (!parseDepCtr(DepCtr, UsedOprMask)) in parseDepCtr()7332 if (!parseExpr(DepCtr)) in parseDepCtr()7336 Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc)); in parseDepCtr()
1719 using namespace llvm::AMDGPU::DepCtr; in printDepCtr()