Home
last modified time | relevance | path

Searched refs:Demanded (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DBDCE.cpp118 APInt Demanded = DB.getDemandedBits(SE); in bitTrackingDCE() local
122 if (Demanded.countl_zero() >= (DestBitSize - SrcBitSize)) { in bitTrackingDCE()
136 APInt Demanded = DB.getDemandedBits(BO); in bitTrackingDCE() local
137 if (!Demanded.isAllOnes()) { in bitTrackingDCE()
144 CanBeSimplified = !Demanded.intersects(*Mask); in bitTrackingDCE()
147 CanBeSimplified = Demanded.isSubsetOf(*Mask); in bitTrackingDCE()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp1193 DemandedFields &Demanded) { in adjustIncoming() argument
1196 if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid() && in adjustIncoming()
1201 Demanded.LMUL = DemandedFields::LMULEqual; in adjustIncoming()
1215 DemandedFields Demanded = getDemanded(MI, ST); in transferBefore() local
1219 if (Info.isValid() && !needVSETVLI(Demanded, NewInfo, Info)) in transferBefore()
1226 const VSETVLIInfo IncomingInfo = adjustIncoming(PrevInfo, NewInfo, Demanded); in transferBefore()
1237 if (Demanded.VLAny || (Demanded.VLZeroness && !EquallyZero)) in transferBefore()
1241 ((Demanded.LMUL || Demanded.SEWLMULRatio) ? IncomingInfo : Info) in transferBefore()
1243 ((Demanded.SEW || Demanded.SEWLMULRatio) ? IncomingInfo : Info).getSEW(), in transferBefore()
1246 (Demanded.TailPolicy ? IncomingInfo : Info).getTailAgnostic() || in transferBefore()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp37 const APInt &Demanded) { in ShrinkDemandedConstant() argument
48 if (C->isSubsetOf(Demanded)) in ShrinkDemandedConstant()
52 I->setOperand(OpNo, ConstantInt::get(Op->getType(), *C & Demanded)); in ShrinkDemandedConstant()
1475 APInt Demanded, APInt &Undef) { in SimplifyDemandedVectorElts() argument
1478 if (Value *V = SimplifyDemandedVectorElts(Op, Demanded, Undef, Depth + 1)) { in SimplifyDemandedVectorElts()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3731 APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24); in simplifyMul24() local
3736 SDValue DemandedLHS = TLI.SimplifyMultipleUseDemandedBits(LHS, Demanded, DAG); in simplifyMul24()
3737 SDValue DemandedRHS = TLI.SimplifyMultipleUseDemandedBits(RHS, Demanded, DAG); in simplifyMul24()
3745 if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI)) in simplifyMul24()
3747 if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI)) in simplifyMul24()
5225 APInt Demanded = APInt::getBitsSet(32, in PerformDAGCombine() local
5233 if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) || in PerformDAGCombine()
5234 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) { in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp2812 auto GetDemandedBitsLHSMask = [&](APInt Demanded, in SimplifyDemandedBits()
2815 Demanded.clearHighBits(KnownRHS.countMinTrailingZeros()); in SimplifyDemandedBits()
2816 return Demanded; in SimplifyDemandedBits()
H A DDAGCombiner.cpp26028 APInt &Demanded = M < (int)NumElts ? DemandedLHS : DemandedRHS; in visitVECTOR_SHUFFLE() local
26029 Demanded.setBit(M % NumElts); in visitVECTOR_SHUFFLE()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp20222 unsigned Demanded = DemandedBits.getZExtValue(); in targetShrinkDemandedConstant() local
20223 unsigned ShrunkMask = Mask & Demanded; in targetShrinkDemandedConstant()
20224 unsigned ExpandedMask = Mask | ~Demanded; in targetShrinkDemandedConstant()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2168 const APInt &Demanded, in optimizeLogicalImm() argument
2181 uint64_t DemandedBits = Demanded.getZExtValue(); in optimizeLogicalImm()
2236 assert(((OldImm ^ NewImm) & Demanded.getZExtValue()) == 0 && in optimizeLogicalImm()