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Searched refs:Demanded (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DBDCE.cpp118 APInt Demanded = DB.getDemandedBits(SE); in bitTrackingDCE() local
122 if (Demanded.countl_zero() >= (DestBitSize - SrcBitSize)) { in bitTrackingDCE()
136 APInt Demanded = DB.getDemandedBits(BO); in bitTrackingDCE() local
137 if (!Demanded.isAllOnes()) { in bitTrackingDCE()
144 CanBeSimplified = !Demanded.intersects(*Mask); in bitTrackingDCE()
147 CanBeSimplified = Demanded.isSubsetOf(*Mask); in bitTrackingDCE()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertVSETVLI.cpp1172 DemandedFields &Demanded) { in adjustIncoming() argument
1175 if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid() && in adjustIncoming()
1180 Demanded.LMUL = DemandedFields::LMULEqual; in adjustIncoming()
1205 DemandedFields Demanded = getDemanded(MI, ST); in transferBefore() local
1209 if (Info.isValid() && !needVSETVLI(Demanded, NewInfo, Info)) in transferBefore()
1216 const VSETVLIInfo IncomingInfo = adjustIncoming(PrevInfo, NewInfo, Demanded); in transferBefore()
1227 if (Demanded.VLAny || (Demanded.VLZeroness && !EquallyZero)) in transferBefore()
1231 ((Demanded.LMUL || Demanded.SEWLMULRatio) ? IncomingInfo : Info) in transferBefore()
1233 ((Demanded.SEW || Demanded.SEWLMULRatio) ? IncomingInfo : Info).getSEW(), in transferBefore()
1236 (Demanded.TailPolicy ? IncomingInfo : Info).getTailAgnostic() || in transferBefore()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp43 const APInt &Demanded) { in ShrinkDemandedConstant() argument
54 if (C->isSubsetOf(Demanded)) in ShrinkDemandedConstant()
58 I->setOperand(OpNo, ConstantInt::get(Op->getType(), *C & Demanded)); in ShrinkDemandedConstant()
1479 APInt Demanded, APInt &Undef) { in SimplifyDemandedVectorElts() argument
1482 if (Value *V = SimplifyDemandedVectorElts(Op, Demanded, Undef, Depth + 1)) { in SimplifyDemandedVectorElts()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3795 APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24); in simplifyMul24() local
3800 SDValue DemandedLHS = TLI.SimplifyMultipleUseDemandedBits(LHS, Demanded, DAG); in simplifyMul24()
3801 SDValue DemandedRHS = TLI.SimplifyMultipleUseDemandedBits(RHS, Demanded, DAG); in simplifyMul24()
3809 if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI)) in simplifyMul24()
3811 if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI)) in simplifyMul24()
5458 APInt Demanded = APInt::getBitsSet(32, in PerformDAGCombine() local
5466 if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) || in PerformDAGCombine()
5467 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) { in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp2880 auto GetDemandedBitsLHSMask = [&](APInt Demanded, in SimplifyDemandedBits()
2883 Demanded.clearHighBits(KnownRHS.countMinTrailingZeros()); in SimplifyDemandedBits()
2884 return Demanded; in SimplifyDemandedBits()
H A DDAGCombiner.cpp27120 APInt &Demanded = M < (int)NumElts ? DemandedLHS : DemandedRHS; in visitVECTOR_SHUFFLE() local
27121 Demanded.setBit(M % NumElts); in visitVECTOR_SHUFFLE()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp20156 unsigned Demanded = DemandedBits.getZExtValue(); in targetShrinkDemandedConstant() local
20157 unsigned ShrunkMask = Mask & Demanded; in targetShrinkDemandedConstant()
20158 unsigned ExpandedMask = Mask | ~Demanded; in targetShrinkDemandedConstant()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2405 const APInt &Demanded, in optimizeLogicalImm() argument
2418 uint64_t DemandedBits = Demanded.getZExtValue(); in optimizeLogicalImm()
2473 assert(((OldImm ^ NewImm) & Demanded.getZExtValue()) == 0 && in optimizeLogicalImm()