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Searched refs:Defs (Results 1 – 25 of 201) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrSystem.td25 let hasSideEffects = 1, Defs = [CC] in {
29 let Predicates = [FeatureBEAREnhancement], hasSideEffects = 1, Defs = [CC] in
33 let Uses = [R2L], Defs = [R2L] in
135 let hasSideEffects = 1, Defs = [CC] in
139 let hasSideEffects = 1, Defs = [CC] in
155 let hasSideEffects = 1, mayStore = 1, Uses = [R0D], Defs = [R0D, CC] in
159 let mayLoad = 1, mayStore = 1, Defs = [CC] in {
181 let Predicates = [FeatureEnhancedDAT2], hasSideEffects = 1, Defs = [CC] in
189 let hasSideEffects = 1, Defs = [CC] in {
195 let hasSideEffects = 1, Defs = [CC] in
[all …]
H A DSystemZInstrDFP.td22 let Uses = [FPC], Defs = [CC] in {
66 let Uses = [FPC], Defs = [CC] in {
78 let Uses = [FPC], Defs = [CC] in {
116 let Defs = [CC, R1L, F0Q], Uses = [FPC, R0L, F4Q] in
145 let Uses = [FPC], Defs = [CC] in {
157 let Uses = [FPC], Defs = [CC] in {
216 let Uses = [FPC], Defs = [CC] in {
222 let Uses = [FPC], Defs = [CC] in {
228 let Defs = [CC] in {
234 let Defs = [CC] in {
[all …]
H A DSystemZInstrHFP.td21 let Defs = [CC] in {
60 let Defs = [CC] in {
71 let Defs = [CC] in {
77 let Defs = [CC] in {
88 let Defs = [CC] in {
95 let Defs = [CC] in {
102 let Defs = [CC] in {
131 let Defs = [CC] in {
142 let Defs = [CC] in {
152 let Defs = [CC] in {
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H A DSystemZInstrInfo.td35 let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1,
41 let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1,
45 let Defs = [R3D, CC], Uses = [R3D, R4D], hasNoSchedulingInfo = 1,
137 let Defs = [CC] in {
161 let Defs = [CC] in {
195 let Defs = [CC] in {
210 let Defs = [CC] in {
277 let isCall = 1, Defs = [CC] in {
289 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in {
296 let isCall = 1, Defs = [R3D, CC], Uses = [FPC] in {
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp63 bool canBundle(const MachineInstr &MI, const RegUse &Defs,
66 void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
67 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
150 bool SIFormMemoryClauses::canBundle(const MachineInstr &MI, const RegUse &Defs, in canBundle() argument
168 const RegUse &Map = MO.isDef() ? Uses : Defs; in canBundle()
217 RegUse &Defs, RegUse &Uses) const { in collectRegUses() argument
228 RegUse &Map = MO.isDef() ? Defs : Uses; in collectRegUses()
245 RegUse &Defs, RegUse &Uses, in processRegUses() argument
247 if (!canBundle(MI, Defs, Uses)) in processRegUses()
253 collectRegUses(MI, Defs, Uses); in processRegUses()
[all …]
H A DSIPostRABundler.cpp49 SmallSet<Register, 16> Defs; member in __anon5d3e08d40111::SIPostRABundler
83 for (Register Def : Defs) in isDependentLoad()
152 assert(Defs.empty()); in runOnMachineFunction()
155 Defs.insert(I->defs().begin()->getReg()); in runOnMachineFunction()
167 Defs.insert(I->defs().begin()->getReg()); in runOnMachineFunction()
220 Defs.clear(); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses; member
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses() argument
164 expandReg(R, Defs); in getDefsUses()
173 BitVector &Set = MO.isDef() ? Defs : Uses; in getDefsUses()
182 BitVector Defs(NR), Uses(NR); in buildMaps() local
186 Defs.reset(); in buildMaps()
188 getDefsUses(&MI, Defs, Uses); in buildMaps()
189 DUM.insert(std::make_pair(Index, DefUseInfo(Defs, Uses))); in buildMaps()
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H A DHexagonPseudo.td81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
91 Defs = [PC, LC0], Uses = [SA0, LC0] in {
98 Defs = [PC, LC1], Uses = [SA1, LC1] in {
105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
149 let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
156 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
177 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
182 Defs = [PC, R31, R6, R7, P0] in
204 let hasSideEffects = 1, isCall = 1, Defs = [R0, R14, R15, R28, R29, R30, R31, PC] in
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp68 RegisterSet &Defs, RegisterSet &Uses);
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, in INITIALIZE_PASS()
105 InsertUsesDefs(LocalDefs, Defs); in INITIALIZE_PASS()
137 RegisterSet &Defs, RegisterSet &Uses) { in MoveCopyOutOfITBlock() argument
151 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
195 RegisterSet Defs, Uses; in InsertITInstructions() local
208 Defs.clear(); in InsertITInstructions()
210 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
252 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
262 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td98 class Defs<list<Register> Regs> {
99 list<Register> Defs = Regs;
557 Defs<[DSPOutFlag20]>;
561 IsCommutable, Defs<[DSPOutFlag20]>;
565 Defs<[DSPOutFlag20]>;
569 Defs<[DSPOutFlag20]>;
573 Defs<[DSPOutFlag20]>;
577 IsCommutable, Defs<[DSPOutFlag20]>;
581 Defs<[DSPOutFlag20]>;
585 Defs<[DSPOutFlag20]>;
[all …]
H A DMipsDelaySlotFiller.cpp136 BitVector Defs, Uses; member in __anon27a8e2d60111::RegDefsUses
202 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anon27a8e2d60111::MemDefsUses
343 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} in RegDefsUses()
352 Defs.set(Mips::RA); in init()
358 Defs.reset(Mips::AT); in init()
370 Defs.set(Mips::RA); in setCallerSaved()
371 Defs.set(Mips::RA_64); in setCallerSaved()
385 Defs |= CallerSavedRegs; in setCallerSaved()
398 Defs |= AllocSet.flip(); in setUnallocatableRegs()
426 Defs |= NewDefs; in update()
[all …]
H A DMicroMipsDSPInstrInfo.td189 "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
191 "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
193 "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
227 Defs<[DSPOutFlag22]>;
230 Defs<[DSPOutFlag22]>;
233 Defs<[DSPOutFlag22]>;
236 Defs<[DSPOutFlag22]>;
261 "shllv.ph", int_mips_shll_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
264 Defs<[DSPOutFlag22]>;
266 "shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBoolRetToInt.cpp74 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
77 Defs.insert(V); in findAllDefs()
85 if (Defs.insert(Op).second) in findAllDefs()
88 return Defs; in findAllDefs()
221 auto Defs = findAllDefs(U); in runOnUse() local
224 if (llvm::none_of(Defs, [](Value *V) { return isa<Instruction>(V); })) in runOnUse()
230 for (Value *V : Defs) in runOnUse()
235 for (Value *V : Defs) in runOnUse()
246 for (Value *V : Defs) in runOnUse()
/freebsd/contrib/llvm-project/clang/utils/TableGen/
H A DSveEmitter.cpp1242 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createCoreHeaderIntrinsics() local
1245 createIntrinsic(R, Defs); in createCoreHeaderIntrinsics()
1251 std::stable_sort(Defs.begin(), Defs.end(), in createCoreHeaderIntrinsics()
1263 for (auto &I : Defs) in createCoreHeaderIntrinsics()
1446 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createBuiltins() local
1448 createIntrinsic(R, Defs); in createBuiltins()
1451 llvm::sort(Defs, [](const std::unique_ptr<Intrinsic> &A, in createBuiltins()
1457 for (auto &Def : Defs) { in createBuiltins()
1488 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createCodeGenMap() local
1490 createIntrinsic(R, Defs); in createCodeGenMap()
[all …]
H A DNeonEmitter.cpp552 void genBuiltinsDef(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs);
554 SmallVectorImpl<Intrinsic *> &Defs);
556 SmallVectorImpl<Intrinsic *> &Defs);
558 SmallVectorImpl<Intrinsic *> &Defs);
2006 SmallVectorImpl<Intrinsic *> &Defs) { in genBuiltinsDef() argument
2013 for (auto *Def : Defs) { in genBuiltinsDef()
2040 raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs) { in genStreamingSVECompatibleList() argument
2044 for (auto *Def : Defs) { in genStreamingSVECompatibleList()
2066 SmallVectorImpl<Intrinsic *> &Defs) { in genOverloadTypeCheckCode() argument
2080 for (auto *Def : Defs) { in genOverloadTypeCheckCode()
[all …]
H A DRISCVVEmitter.cpp417 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createBuiltins() local
418 createRVVIntrinsics(Defs); in createBuiltins()
427 for (auto &Def : Defs) { in createBuiltins()
448 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createCodeGen() local
449 createRVVIntrinsics(Defs); in createCodeGen()
451 llvm::stable_sort(Defs, [](const std::unique_ptr<RVVIntrinsic> &A, in createCodeGen()
463 RVVIntrinsic *PrevDef = Defs.begin()->get(); in createCodeGen()
464 for (auto &Def : Defs) { in createCodeGen()
494 emitCodeGenSwitchBody(Defs.back().get(), OS); in createCodeGen()
746 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createSema() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSNP.td19 let Uses = [RAX], Defs = [EAX, EFLAGS] in
24 let Uses = [RAX, RCX, RDX], Defs = [EAX, EFLAGS] in
28 let Uses = [EAX, ECX, EDX], Defs = [EAX, EFLAGS] in
33 let Uses = [RAX, RCX], Defs = [EAX, EFLAGS] in
38 let Uses = [RAX, RCX, RDX], Defs = [EAX, EFLAGS] in
43 let Uses = [RAX, RDX], Defs = [RAX, RCX, RDX, EFLAGS] in
H A DX86InstrMisc.td41 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
45 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
59 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
116 SchedRW = [WriteRMW], Defs = [ESP] in {
130 let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in
135 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in
141 let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
148 let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0,
155 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
200 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
[all …]
H A DX86InstrKL.td45 let Uses = [XMM0, EAX], Defs = [EFLAGS], Predicates = [HasKL] in {
52 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in
55 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
58 let Constraints = "$src1 = $dst", Defs = [EFLAGS] in
71 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], mayLoad = 1 in {
H A DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
73 let hasSideEffects = 1, Defs = [RSP, EFLAGS] in {
78 } // hasSideEffects = 1, Defs = [RSP, EFLAGS]
90 let Defs = [AL], Uses = [DX] in
92 let Defs = [AX], Uses = [DX] in
95 let Defs = [EAX], Uses = [DX] in
99 let Defs = [AL] in
102 let Defs = [AX] in
105 let Defs = [EAX] in
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DMemorySSAUpdater.cpp148 auto *Defs = MSSA->getWritableBlockDefs(MA->getBlock()); in getPreviousDefInBlock() local
151 if (Defs) { in getPreviousDefInBlock()
156 if (Iter != Defs->rend()) in getPreviousDefInBlock()
175 auto *Defs = MSSA->getWritableBlockDefs(BB); in getPreviousDefFromEnd() local
177 if (Defs) { in getPreviousDefFromEnd()
178 CachedPreviousDef.insert({BB, &*Defs->rbegin()}); in getPreviousDefFromEnd()
179 return &*Defs->rbegin(); in getPreviousDefFromEnd()
257 auto *Defs = MSSA->getBlockDefs(MU->getBlock()); in insertUse() local
258 (void)Defs; in insertUse()
259 assert((!Defs || (++Defs->begin() == Defs->end())) && in insertUse()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp46 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
47 Defs[Hexagon::LC0].insert(Unconditional); in init()
50 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
51 Defs[Hexagon::LC1].insert(Unconditional); in init()
131 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
182 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
390 if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) { in checkPredicates()
403 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates()
530 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly() local
531 for (unsigned j = 0; j < Defs; ++j) { in checkRegistersReadOnly()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp463 SmallVectorImpl<unsigned> &Defs) { in HandlePhysRegDef() argument
498 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
502 SmallVectorImpl<unsigned> &Defs) { in UpdatePhysRegDefs() argument
503 while (!Defs.empty()) { in UpdatePhysRegDefs()
504 Register Reg = Defs.pop_back_val(); in UpdatePhysRegDefs()
513 SmallVectorImpl<unsigned> &Defs, in runOnInstr() argument
570 HandlePhysRegDef(MOReg, &MI, Defs); in runOnInstr()
572 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
577 SmallVector<unsigned, 4> Defs; in runOnBlock() local
581 HandlePhysRegDef(LI.PhysReg, nullptr, Defs); in runOnBlock()
[all …]
H A DReachingDefAnalysis.cpp401 InstSet &Defs) const { in getGlobalReachingDefs()
403 Defs.insert(Def); in getGlobalReachingDefs()
408 getLiveOuts(MBB, PhysReg, Defs); in getGlobalReachingDefs()
412 MCRegister PhysReg, InstSet &Defs) const { in getLiveOuts()
414 getLiveOuts(MBB, PhysReg, Defs, VisitedBBs); in getLiveOuts()
418 MCRegister PhysReg, InstSet &Defs, in getLiveOuts() argument
430 Defs.insert(Def); in getLiveOuts()
433 getLiveOuts(Pred, PhysReg, Defs, VisitedBBs); in getLiveOuts()
560 SmallSet<int, 2> Defs; in isSafeToMove() local
566 Defs.insert(MO.getReg()); in isSafeToMove()
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DCTagsEmitter.cpp73 const auto &Defs = Records.getDefs(); in run() local
76 Tags.reserve(Classes.size() + Defs.size()); in run()
82 for (const auto &D : Defs) in run()

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