Searched refs:DefSize (Results 1 – 5 of 5) sorted by relevance
24 TypeSize DefSize = TargetTransformInfoImplBase::getRegisterBitWidth(K); in getRegisterBitWidth() local35 return DefSize; in getRegisterBitWidth()
837 unsigned DefSize = MRI.getType(DefReg).getSizeInBits(); in findValueFromDefImpl() local841 DefStartBit += DefSize; in findValueFromDefImpl()851 if (StartBit == 0 && Size == DefSize) in findValueFromDefImpl()
2609 const unsigned DefSize = DefTy.getSizeInBits(); in select() local2632 if (DefSize != 128 && I.getOperand(1).getFPImm()->isExactlyValue(0.0)) in select()2654 switch (DefSize) { in select()2664 EVT::getFloatingPointVT(DefSize), OptForSize)) in select()2682 assert((DefSize == 32 || DefSize == 64) && "Unexpected const def size"); in select()2685 DefSize == 32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in select()2709 DefSize == 64 ? AArch64::MOVi64imm : AArch64::MOVi32imm; in select()3611 Register DefSize = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectMOPS() local3613 MIB.buildInstr(Mopcode, {DefDstPtr, DefSize}, in selectMOPS()3617 MIB.buildInstr(Mopcode, {DefDstPtr, DefSrcPtr, DefSize}, in selectMOPS()
1422 unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); in selectUnmergeValues() local1429 .addImm(Idx * DefSize); in selectUnmergeValues()