Searched refs:DefSU (Results 1 – 3 of 3) sorted by relevance
335 SUnit *DefSU = I->SU; in addPhysRegDeps() local336 if (DefSU == &ExitSU) in addPhysRegDeps()338 MachineInstr *DefInstr = DefSU->getInstr(); in addPhysRegDeps()340 if (DefSU != SU && in addPhysRegDeps()347 ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep, in addPhysRegDeps()349 DefSU->addPred(Dep); in addPhysRegDeps()511 SUnit *DefSU = V2SU.SU; in addVRegDefDeps() local517 if (DefSU == SU) in addVRegDefDeps()521 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()522 DefSU->addPred(Dep); in addVRegDefDeps()[all …]
1287 SUnit *DefSU = getSUnit(DefMI); in changeDependences() local1288 if (!DefSU) in changeDependences()1304 if (P.getSUnit() == DefSU) in changeDependences()3412 SUnit *DefSU = Insts.at(MoveDef); in orderDependence() local3422 orderDependence(SSD, DefSU, Insts); in orderDependence()3439 SUnit *DefSU = SSD->getSUnit(&Phi); in isLoopCarried() local3440 unsigned DefCycle = cycleScheduled(DefSU); in isLoopCarried()3441 int DefStage = stageScheduled(DefSU); in isLoopCarried()
1848 const SUnit *DefSU = getSUnit(DefMI); in computeCyclicCriticalPath() local1849 if (!DefSU) in computeCyclicCriticalPath()1852 unsigned LiveOutHeight = DefSU->getHeight(); in computeCyclicCriticalPath()1853 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency; in computeCyclicCriticalPath()1873 unsigned LiveInHeight = SU->getHeight() + DefSU->Latency; in computeCyclicCriticalPath()1880 LLVM_DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU(" in computeCyclicCriticalPath()