Searched refs:DefRegs (Results 1 – 10 of 10) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 115 SmallVector<MCRegister, 4> DefRegs; member
200 markRegsUnavailable(I->second.DefRegs, TRI); in clobberRegUnit()
229 for (auto itr = SrcCopy->second.DefRegs.begin(); in clobberRegUnit()
230 itr != SrcCopy->second.DefRegs.end(); itr++) { in clobberRegUnit()
232 SrcCopy->second.DefRegs.erase(itr); in clobberRegUnit()
238 if (SrcCopy->second.DefRegs.empty() && !SrcCopy->second.MI) { in clobberRegUnit()
315 if (!is_contained(Copy.DefRegs, Def)) in trackCopy()
316 Copy.DefRegs.push_back(Def); in trackCopy()
341 if (CI->second.DefRegs.size() != 1) in findCopyDefViaUnit()
343 MCRegUnit RU = *TRI.regunits(CI->second.DefRegs[0]).begin(); in findCopyDefViaUnit()
|
| H A D | LiveVariables.cpp | 519 SmallVector<Register, 4> DefRegs; in runOnInstr() local
541 DefRegs.push_back(MOReg); in runOnInstr()
559 for (Register MOReg : DefRegs) { in runOnInstr()
|
| H A D | MachineOutliner.cpp | 1134 SmallSet<Register, 2> UseRegs, DefRegs; in outline() local
1154 DefRegs.insert(MOP.getReg()); in outline()
1171 for (const Register &I : DefRegs) in outline()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 2139 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0)); in applyMappingSMULU64() local
2144 if (DefRegs.empty()) { in applyMappingSMULU64()
2150 assert(DefRegs.size() == 2); in applyMappingSMULU64()
2173 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingSMULU64()
2197 B.buildAdd(DefRegs[1], Add, MulHiLo); in applyMappingSMULU64()
2198 B.buildMul(DefRegs[0], Src0Regs[0], Src1Regs[0]); in applyMappingSMULU64()
2222 SmallVector<Register, 1> DefRegs(OpdMapper.getVRegs(0)); in applyMappingImpl() local
2223 if (DefRegs.empty()) in applyMappingImpl()
2224 DefRegs.push_back(DstReg); in applyMappingImpl()
2239 B.buildTrunc(DefRegs[0], NewDstReg); in applyMappingImpl()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 455 std::set<RegisterRef> DefRegs; in updateDeadsInRange() local
465 DefRegs.insert(Op); in updateDeadsInRange()
485 if (!Op.isReg() || !DefRegs.count(Op)) in updateDeadsInRange()
|
| H A D | HexagonConstPropagation.cpp | 2845 SmallVector<unsigned,2> DefRegs; in rewriteHexConstDefs() local
2854 DefRegs.push_back(R); in rewriteHexConstDefs()
2867 for (unsigned R : DefRegs) { in rewriteHexConstDefs()
2958 AllDefs = (ChangedNum == DefRegs.size()); in rewriteHexConstDefs()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.td | 1693 list<Register> DefRegs> :
1697 let Defs = DefRegs;
1729 list<Register> DefRegs> :
1732 let Defs = DefRegs;
1753 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1756 let Defs = DefRegs;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2634 DenseSet<Register> DefRegs; in emitSjLjDispatchBlock() local
2637 DefRegs.insert(MOp.getReg()); in emitSjLjDispatchBlock()
2642 if (!DefRegs.contains(Reg)) in emitSjLjDispatchBlock()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 11356 DenseSet<unsigned> DefRegs; in EmitSjLjDispatchBlock() local
11361 DefRegs.insert(OI->getReg()); in EmitSjLjDispatchBlock()
11376 if (!DefRegs.contains(Reg)) in EmitSjLjDispatchBlock()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 37689 DenseSet<Register> DefRegs; in EmitSjLjDispatchBlock() local
37692 DefRegs.insert(MOp.getReg()); in EmitSjLjDispatchBlock()
37697 if (!DefRegs.contains(Reg)) in EmitSjLjDispatchBlock()
|