Searched refs:DefRegs (Results 1 – 10 of 10) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 112 SmallVector<MCRegister, 4> DefRegs; member
173 markRegsUnavailable(I->second.DefRegs, TRI); in clobberRegister()
202 for (auto itr = SrcCopy->second.DefRegs.begin(); in clobberRegister()
203 itr != SrcCopy->second.DefRegs.end(); itr++) { in clobberRegister()
205 SrcCopy->second.DefRegs.erase(itr); in clobberRegister()
211 if (SrcCopy->second.DefRegs.empty() && !SrcCopy->second.MI) { in clobberRegister()
245 if (!is_contained(Copy.DefRegs, Def)) in trackCopy()
246 Copy.DefRegs.push_back(Def); in trackCopy()
271 if (CI->second.DefRegs.size() != 1) in findCopyDefViaUnit()
273 MCRegUnit RU = *TRI.regunits(CI->second.DefRegs[0]).begin(); in findCopyDefViaUnit()
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| H A D | MachineOutliner.cpp | 921 SmallSet<Register, 2> UseRegs, DefRegs; in outline() local
941 DefRegs.insert(MOP.getReg()); in outline()
958 for (const Register &I : DefRegs) in outline()
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| H A D | LiveVariables.cpp | 526 SmallVector<unsigned, 4> DefRegs; in runOnInstr() local
548 DefRegs.push_back(MOReg); in runOnInstr()
566 for (unsigned MOReg : DefRegs) { in runOnInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1138 SmallVector<Register, 16> DefRegs(OpdMapper.getVRegs(0)); in applyMappingLoad() local
2111 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0)); in applyMappingSMULU64() local
2116 if (DefRegs.empty()) { in applyMappingSMULU64()
2122 assert(DefRegs.size() == 2); in applyMappingSMULU64()
2145 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingSMULU64()
2169 B.buildAdd(DefRegs[1], Add, MulHiLo); in applyMappingSMULU64()
2170 B.buildMul(DefRegs[0], Src0Regs[0], Src1Regs[0]); in applyMappingSMULU64()
2194 SmallVector<Register, 1> DefRegs(OpdMapper.getVRegs(0)); in applyMappingImpl() local
2195 if (DefRegs.empty()) in applyMappingImpl()
2196 DefRegs.push_back(DstReg); in applyMappingImpl()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 472 std::set<RegisterRef> DefRegs; in updateDeadsInRange() local
482 DefRegs.insert(Op); in updateDeadsInRange()
502 if (!Op.isReg() || !DefRegs.count(Op)) in updateDeadsInRange()
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| H A D | HexagonConstPropagation.cpp | 2841 SmallVector<unsigned,2> DefRegs; in rewriteHexConstDefs() local
2850 DefRegs.push_back(R); in rewriteHexConstDefs()
2863 for (unsigned R : DefRegs) { in rewriteHexConstDefs()
2954 AllDefs = (ChangedNum == DefRegs.size()); in rewriteHexConstDefs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.td | 1681 list<Register> DefRegs> :
1685 let Defs = DefRegs;
1717 list<Register> DefRegs> :
1720 let Defs = DefRegs;
1741 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1744 let Defs = DefRegs;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2650 DenseMap<Register, bool> DefRegs; in emitSjLjDispatchBlock() local
2653 DefRegs[MOp.getReg()] = true; in emitSjLjDispatchBlock()
2658 if (!DefRegs[Reg]) in emitSjLjDispatchBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 11293 DenseMap<unsigned, bool> DefRegs; in EmitSjLjDispatchBlock() local
11298 DefRegs[OI->getReg()] = true; in EmitSjLjDispatchBlock()
11313 if (!DefRegs[Reg]) in EmitSjLjDispatchBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 36470 DenseMap<unsigned, bool> DefRegs; in EmitSjLjDispatchBlock() local
36473 DefRegs[MOp.getReg()] = true; in EmitSjLjDispatchBlock()
36478 if (!DefRegs[Reg]) in EmitSjLjDispatchBlock()
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