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Searched refs:DefReg (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp169 Register DefReg = Def.getReg(); in transferUsedLanes() local
170 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
204 Register DefReg = Def.getReg(); in transferDefinedLanesStep() local
205 if (!DefReg.isVirtual()) in transferDefinedLanesStep()
207 unsigned DefRegIdx = Register::virtReg2Index(DefReg); in transferDefinedLanesStep()
347 Register DefReg = Def.getReg(); in determineInitialUsedLanes() local
350 if (DefReg.isVirtual()) { in determineInitialUsedLanes()
354 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
433 Register DefReg = Def.getReg(); in isUndefInput() local
434 if (!DefReg.isVirtual()) in isUndefInput()
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H A DTailDuplicator.cpp361 Register DefReg = MI->getOperand(0).getReg(); in processPHI() local
366 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI()
367 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
373 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI()
374 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
H A DMachineSink.cpp389 Register DefReg; in PerformSinkAndFold() local
405 if (DefReg) in PerformSinkAndFold()
407 DefReg = Reg; in PerformSinkAndFold()
435 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in PerformSinkAndFold()
441 Worklist.push_back(DefReg); in PerformSinkAndFold()
567 Worklist.push_back(DefReg); in PerformSinkAndFold()
1967 for (auto DefReg : DefedRegsInCopy) { in getSingleLiveInSuccBB() local
1969 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI); in getSingleLiveInSuccBB()
2002 for (unsigned DefReg : DefedRegsInCopy) in updateLiveIn() local
2003 for (MCPhysReg S : TRI->subregs_inclusive(DefReg)) in updateLiveIn()
H A DImplicitNullChecks.cpp716 unsigned DefReg = NoRegister; in insertFaultingInstr() local
718 DefReg = MI->getOperand(0).getReg(); in insertFaultingInstr()
729 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg) in insertFaultingInstr()
H A DMachineLICM.cpp1338 Register DefReg = MI.getOperand(0).getReg(); in IsProfitableToHoist() local
1339 if (DefReg.isVirtual() && in IsProfitableToHoist()
1346 any_of(MRI->use_nodbg_instructions(DefReg), in IsProfitableToHoist()
1347 [&CurLoop, this, DefReg, Cost](MachineInstr &UseMI) { in IsProfitableToHoist()
1356 !CurLoop->isLoopInvariant(UseMI, DefReg)) in IsProfitableToHoist()
H A DLiveVariables.cpp243 Register DefReg = MO.getReg(); in FindLastPartialDef() local
244 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
245 for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg)) in FindLastPartialDef()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h462 Register DefReg = MI.getOperand(I).getReg(); in tryFoldUnmergeCast() local
463 UpdatedDefs.push_back(DefReg); in tryFoldUnmergeCast()
464 Builder.buildTrunc(DefReg, NewUnmerge.getReg(I)); in tryFoldUnmergeCast()
823 Register findValueFromDefImpl(Register DefReg, unsigned StartBit, in findValueFromDefImpl() argument
826 getDefSrcRegIgnoringCopies(DefReg, MRI); in findValueFromDefImpl()
828 DefReg = DefSrcReg->Reg; in findValueFromDefImpl()
837 unsigned DefSize = MRI.getType(DefReg).getSizeInBits(); in findValueFromDefImpl()
839 if (MO.getReg() == DefReg) in findValueFromDefImpl()
852 return DefReg; in findValueFromDefImpl()
880 Register findValueFromDef(Register DefReg, unsigned StartBit, in findValueFromDef() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp474 Register DefReg = MO.getReg(); in oneUseDominatesOtherUses() local
475 if (!DefReg.isVirtual() || !MFI.isVRegStackified(DefReg)) in oneUseDominatesOtherUses()
477 assert(MRI.hasOneNonDBGUse(DefReg)); in oneUseDominatesOtherUses()
478 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg); in oneUseDominatesOtherUses()
643 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse() local
655 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
657 DefDIs.updateReg(DefReg); in moveAndTeeForMultiUse()
671 LIS.createAndComputeVirtRegInterval(DefReg); in moveAndTeeForMultiUse()
672 MFI.stackifyVReg(MRI, DefReg); in moveAndTeeForMultiUse()
917 Register DefReg = SubsequentDef->getReg(); in runOnMachineFunction() local
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H A DWebAssemblyExplicitLocals.cpp202 for (auto DefReg : Def->defs()) { in findStartOfTree() local
203 if (!MFI.isVRegStackified(DefReg.getReg())) { in findStartOfTree()
310 Register DefReg = MI.getOperand(2).getReg(); in runOnMachineFunction() local
311 const TargetRegisterClass *RC = MRI.getRegClass(DefReg); in runOnMachineFunction()
314 if (!MFI.isVRegStackified(DefReg)) { in runOnMachineFunction()
315 unsigned LocalId = getLocalId(Reg2Local, MFI, CurLocal, DefReg); in runOnMachineFunction()
H A DWebAssemblyCFGStackify.cpp830 Register DefReg = MI.getOperand(2).getReg(); in unstackifyVRegsUsedInSplitBB() local
833 MFI.unstackifyVReg(DefReg); in unstackifyVRegsUsedInSplitBB()
835 WebAssembly::getCopyOpcodeForRegClass(MRI.getRegClass(DefReg)); in unstackifyVRegsUsedInSplitBB()
837 .addReg(DefReg); in unstackifyVRegsUsedInSplitBB()
838 BuildMI(MBB, &MI, MI.getDebugLoc(), TII.get(CopyOpc), Reg).addReg(DefReg); in unstackifyVRegsUsedInSplitBB()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRedundantCopyElimination.cpp122 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
125 if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) && in optimizeBlock()
126 TargetReg == DefReg) { in optimizeBlock()
H A DRISCVInsertVSETVLI.cpp517 Register DefReg; member
557 AVLRegDef.DefReg = AVLReg; in setAVLRegDef()
572 assert(hasAVLReg() && AVLRegDef.DefReg.isVirtual()); in getAVLReg()
573 return AVLRegDef.DefReg; in getAVLReg()
1688 Register DefReg = NextMI->getOperand(0).getReg(); in coalesceVSETVLIs() local
1690 MI.getOperand(0).setReg(DefReg); in coalesceVSETVLIs()
1695 if (DefReg.isVirtual() && LIS) { in coalesceVSETVLIs()
1696 LiveInterval &DefLI = LIS->getInterval(DefReg); in coalesceVSETVLIs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RedundantCopyElimination.cpp381 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
384 if (!MRI->isReserved(DefReg) && in optimizeBlock()
388 if (KnownReg.Reg != DefReg && in optimizeBlock()
389 !TRI->isSuperRegister(DefReg, KnownReg.Reg)) in optimizeBlock()
413 if (TRI->isSuperRegister(DefReg, KnownReg.Reg) && KnownReg.Imm < 0) in optimizeBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
H A DX86DomainReassignment.cpp592 Register DefReg = DefOp.getReg(); in buildClosure() local
593 if (!DefReg.isVirtual()) { in buildClosure()
597 visitRegister(C, DefReg, Domain, Worklist); in buildClosure()
H A DX86LoadValueInjectionLoadHardening.cpp369 RegisterRef DefReg = Def.Addr->getRegRef(DFG); in getGadgetGraph() local
370 for (auto UseID : L.getAllReachedUses(DefReg, Def)) { in getGadgetGraph()
375 if (DFG.getPRI().alias(RegisterRef(I.first), DefReg)) { in getGadgetGraph()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp568 const Register DefReg = I.getOperand(0).getReg(); in selectLoadStoreOp() local
569 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
570 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
627 addFullAddress(MIB, AM).addUse(DefReg); in selectLoadStoreOp()
651 const Register DefReg = I.getOperand(0).getReg(); in selectFrameIndexOrGep() local
652 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
704 const Register DefReg = I.getOperand(0).getReg(); in selectGlobalValue() local
705 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
723 const Register DefReg = I.getOperand(0).getReg(); in selectConstant() local
724 LLT Ty = MRI.getType(DefReg); in selectConstant()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp144 Register DefReg = ConstMI->getOperand(0).getReg(); in foldConstantsIntoIntrinsics() local
145 if (MRI.use_empty(DefReg) && !TrackedConstRegs.contains(DefReg)) in foldConstantsIntoIntrinsics()
668 Register DefReg; in insertInlineAsmProcess() local
683 DefReg = MO.getReg(); in insertInlineAsmProcess()
688 if (!DefReg.isValid()) { in insertInlineAsmProcess()
689 DefReg = MRI.createGenericVirtualRegister(LLT::scalar(32)); in insertInlineAsmProcess()
690 MRI.setRegClass(DefReg, &SPIRV::IDRegClass); in insertInlineAsmProcess()
693 GR->assignSPIRVTypeToVReg(VoidType, DefReg, MF); in insertInlineAsmProcess()
696 .addDef(DefReg) in insertInlineAsmProcess()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.cpp186 auto DefReg = Inst.getOperand(I).getReg(); in updateState() local
187 if (isGPR(DefReg)) in updateState()
188 setGPRState(DefReg, std::nullopt); in updateState()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp673 Register DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
679 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
726 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
745 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
785 Register DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
787 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
H A DPPCPreEmitPeephole.cpp259 Register DefReg; in addLinkerOpt() member
291 if (!BBI->readsRegister(Pair.DefReg, TRI) && in addLinkerOpt()
292 !BBI->modifiesRegister(Pair.DefReg, TRI)) in addLinkerOpt()
301 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && in addLinkerOpt()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp368 int DefReg = 0; in loadImmediate() local
371 DefReg = MO.getReg(); in loadImmediate()
390 if (DefReg != Reg) { in loadImmediate()
405 if (DefReg!= SpReg) { in loadImmediate()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp520 const Register DefReg = MI.getOperand(0).getReg(); in select() local
521 const LLT DefTy = MRI.getType(DefReg); in select()
524 MRI.getRegClassOrRegBank(DefReg); in select()
543 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
995 Register DefReg = MI.getOperand(0).getReg(); in selectAddr() local
996 const LLT DefTy = MRI.getType(DefReg); in selectAddr()
1022 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {}) in selectAddr()
1050 auto Result = MIB.buildInstr(RISCV::ADDI, {DefReg}, {AddrHiDest}) in selectAddr()
1076 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {}) in selectAddr()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp1585 Register DefReg = Def->getOperand(0).getReg(); in tryFoldClamp() local
1587 if (TRI->isSGPRReg(*MRI, DefReg)) { in tryFoldClamp()
1592 .addReg(DefReg); in tryFoldClamp()
1594 MRI->replaceRegWith(MIDstReg, DefReg); in tryFoldClamp()
2034 Register DefReg = Def.getReg(); in tryFoldLoad() local
2036 if (DefReg.isPhysical() || !TRI->isVGPR(*MRI, DefReg)) in tryFoldLoad()
2041 for (const MachineInstr &I : MRI->use_nodbg_instructions(DefReg)) in tryFoldLoad()
2063 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in tryFoldLoad()
2064 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
2066 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp302 MachineInstr *emitADD(Register DefReg, MachineOperand &LHS,
2314 Register DefReg = I.getOperand(0).getReg(); in earlySelect() local
2315 LLT Ty = MRI.getType(DefReg); in earlySelect()
2318 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in earlySelect()
2321 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI); in earlySelect()
2464 const Register DefReg = I.getOperand(0).getReg(); in select() local
2465 const LLT DefTy = MRI.getType(DefReg); in select()
2468 MRI.getRegClassOrRegBank(DefReg); in select()
2487 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
2607 const Register DefReg = I.getOperand(0).getReg(); in select() local
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