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Searched refs:DefReg (Results 1 – 25 of 49) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankSelect.cpp235 Register DefReg = getVReg(MI.getOperand(0)); in runOnMachineFunction() local
236 if (!DefReg.isValid() || MRI.getRegClassOrNull(DefReg)) in runOnMachineFunction()
239 assert(!MRI.getRegBankOrNull(DefReg)); in runOnMachineFunction()
240 MRI.setRegBank(DefReg, *RBSHelper.getRegBankToAssign(DefReg)); in runOnMachineFunction()
258 Register DefReg = getVReg(DefOP); in runOnMachineFunction() local
259 if (!DefReg.isValid()) in runOnMachineFunction()
262 const RegisterBank *RB = RBSHelper.getRegBankToAssign(DefReg); in runOnMachineFunction()
263 if (MRI.getRegClassOrNull(DefReg)) in runOnMachineFunction()
266 assert(!MRI.getRegBankOrNull(DefReg)); in runOnMachineFunction()
267 MRI.setRegBank(DefReg, *RB); in runOnMachineFunction()
H A DSIFoldOperands.cpp2128 Register DefReg = Def->getOperand(0).getReg(); in tryFoldClamp() local
2130 if (TRI->isSGPRReg(*MRI, DefReg)) { in tryFoldClamp()
2135 .addReg(DefReg); in tryFoldClamp()
2137 MRI->replaceRegWith(MIDstReg, DefReg); in tryFoldClamp()
2580 Register DefReg = Def.getReg(); in tryFoldLoad() local
2582 if (DefReg.isPhysical() || !TRI->isVGPR(*MRI, DefReg)) in tryFoldLoad()
2586 llvm::make_pointer_range(MRI->use_nodbg_instructions(DefReg))); in tryFoldLoad()
2608 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in tryFoldLoad()
2609 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
2611 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp169 Register DefReg = Def.getReg(); in transferUsedLanes() local
170 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
204 Register DefReg = Def.getReg(); in transferDefinedLanesStep() local
205 if (!DefReg.isVirtual()) in transferDefinedLanesStep()
207 unsigned DefRegIdx = DefReg.virtRegIndex(); in transferDefinedLanesStep()
347 Register DefReg = Def.getReg(); in determineInitialUsedLanes() local
350 if (DefReg.isVirtual()) { in determineInitialUsedLanes()
354 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
440 Register DefReg = Def.getReg(); in isUndefInput() local
441 if (!DefReg.isVirtual()) in isUndefInput()
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H A DTailDuplicator.cpp360 Register DefReg = MI->getOperand(0).getReg(); in processPHI() local
365 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI()
366 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
372 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI()
373 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
H A DMachineSink.cpp429 Register DefReg; in PerformSinkAndFold() local
445 if (DefReg) in PerformSinkAndFold()
447 DefReg = Reg; in PerformSinkAndFold()
475 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in PerformSinkAndFold()
481 Worklist.push_back(DefReg); in PerformSinkAndFold()
607 Worklist.push_back(DefReg); in PerformSinkAndFold()
2158 for (auto DefReg : DefedRegsInCopy) { in getSingleLiveInSuccBB() local
2160 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI); in getSingleLiveInSuccBB()
2193 for (Register DefReg : DefedRegsInCopy) in updateLiveIn() local
2194 for (MCPhysReg S : TRI->subregs_inclusive(DefReg)) in updateLiveIn()
H A DImplicitNullChecks.cpp712 Register DefReg; in insertFaultingInstr() local
714 DefReg = MI->getOperand(0).getReg(); in insertFaultingInstr()
725 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg) in insertFaultingInstr()
H A DMachineLICM.cpp1361 Register DefReg = MI.getOperand(0).getReg(); in IsProfitableToHoist() local
1362 if (DefReg.isVirtual() && in IsProfitableToHoist()
1369 any_of(MRI->use_nodbg_instructions(DefReg), in IsProfitableToHoist()
1370 [&CurLoop, this, DefReg, in IsProfitableToHoist()
1380 !CurLoop->isLoopInvariant(UseMI, DefReg)) in IsProfitableToHoist()
H A DLiveVariables.cpp242 Register DefReg = MO.getReg(); in FindLastPartialDef() local
243 if (TRI->isSubRegister(Reg, DefReg)) in FindLastPartialDef()
244 PartDefRegs.insert_range(TRI->subregs_inclusive(DefReg)); in FindLastPartialDef()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h467 Register DefReg = MI.getOperand(I).getReg(); in tryFoldUnmergeCast() local
468 UpdatedDefs.push_back(DefReg); in tryFoldUnmergeCast()
469 Builder.buildTrunc(DefReg, NewUnmerge.getReg(I)); in tryFoldUnmergeCast()
828 Register findValueFromDefImpl(Register DefReg, unsigned StartBit, in findValueFromDefImpl() argument
831 getDefSrcRegIgnoringCopies(DefReg, MRI); in findValueFromDefImpl()
833 DefReg = DefSrcReg->Reg; in findValueFromDefImpl()
842 unsigned DefSize = MRI.getType(DefReg).getSizeInBits(); in findValueFromDefImpl()
844 if (MO.getReg() == DefReg) in findValueFromDefImpl()
857 return DefReg; in findValueFromDefImpl()
885 Register findValueFromDef(Register DefReg, unsigned StartBit, in findValueFromDef() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp500 Register DefReg = MO.getReg(); in oneUseDominatesOtherUses() local
501 if (!DefReg.isVirtual() || !MFI.isVRegStackified(DefReg)) in oneUseDominatesOtherUses()
503 assert(MRI.hasOneNonDBGUse(DefReg)); in oneUseDominatesOtherUses()
504 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg); in oneUseDominatesOtherUses()
672 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse() local
684 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
686 DefDIs.updateReg(DefReg); in moveAndTeeForMultiUse()
700 LIS.createAndComputeVirtRegInterval(DefReg); in moveAndTeeForMultiUse()
701 MFI.stackifyVReg(MRI, DefReg); in moveAndTeeForMultiUse()
958 Register DefReg = SubsequentDef->getReg(); in runOnMachineFunction() local
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H A DWebAssemblyExplicitLocals.cpp202 for (auto DefReg : Def->defs()) { in findStartOfTree() local
203 if (!MFI.isVRegStackified(DefReg.getReg())) { in findStartOfTree()
332 Register DefReg = MI.getOperand(2).getReg(); in runOnMachineFunction() local
333 const TargetRegisterClass *RC = MRI.getRegClass(DefReg); in runOnMachineFunction()
336 if (!MFI.isVRegStackified(DefReg)) { in runOnMachineFunction()
337 unsigned LocalId = getLocalId(Reg2Local, MFI, CurLocal, DefReg); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRedundantCopyElimination.cpp118 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
121 if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) && in optimizeBlock()
122 TargetReg == DefReg) { in optimizeBlock()
H A DRISCVInsertVSETVLI.cpp488 Register DefReg; member
528 AVLRegDef.DefReg = AVLReg; in setAVLRegDef()
543 assert(hasAVLReg() && AVLRegDef.DefReg.isVirtual()); in getAVLReg()
544 return AVLRegDef.DefReg; in getAVLReg()
1700 Register DefReg = NextMI->getOperand(0).getReg(); in coalesceVSETVLIs() local
1702 MI.getOperand(0).setReg(DefReg); in coalesceVSETVLIs()
1716 if (DefReg.isVirtual() && LIS) { in coalesceVSETVLIs()
1717 LiveInterval &DefLI = LIS->getInterval(DefReg); in coalesceVSETVLIs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RedundantCopyElimination.cpp377 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
380 if (!MRI->isReserved(DefReg) && in optimizeBlock()
384 if (KnownReg.Reg != DefReg && in optimizeBlock()
385 !TRI->isSuperRegister(DefReg, KnownReg.Reg)) in optimizeBlock()
409 if (TRI->isSuperRegister(DefReg, KnownReg.Reg) && KnownReg.Imm < 0) in optimizeBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
H A DX86DomainReassignment.cpp598 Register DefReg = DefOp.getReg(); in buildClosure() local
599 if (!DefReg.isVirtual()) { in buildClosure()
603 if (!visitRegister(C, DefReg, Domain, Worklist)) in buildClosure()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp637 const Register DefReg = I.getOperand(0).getReg(); in selectLoadStoreOp() local
638 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
639 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
678 addFullAddress(MIB, AM).addUse(DefReg); in selectLoadStoreOp()
702 const Register DefReg = I.getOperand(0).getReg(); in selectFrameIndexOrGep() local
703 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
732 const Register DefReg = I.getOperand(0).getReg(); in selectGlobalValue() local
733 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
751 const Register DefReg = I.getOperand(0).getReg(); in selectConstant() local
752 LLT Ty = MRI.getType(DefReg); in selectConstant()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombiner.cpp198 Register DefReg = Def.getReg(); in addUsersToWorkList() local
199 if (!DefReg.isVirtual()) in addUsersToWorkList()
201 for (auto &UseMI : MRI.use_nodbg_instructions(DefReg)) { in addUsersToWorkList()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.cpp191 auto DefReg = Inst.getOperand(I).getReg(); in updateState() local
192 if (isGPR(DefReg)) in updateState()
193 setGPRState(DefReg, std::nullopt); in updateState()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp671 Register DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
677 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
724 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
743 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
783 Register DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
785 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
H A DPPCPreEmitPeephole.cpp255 Register DefReg; in addLinkerOpt() member
287 if (!BBI->readsRegister(Pair.DefReg, TRI) && in addLinkerOpt()
288 !BBI->modifiesRegister(Pair.DefReg, TRI)) in addLinkerOpt()
297 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && in addLinkerOpt()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp365 int DefReg = 0; in loadImmediate() local
368 DefReg = MO.getReg(); in loadImmediate()
387 if (DefReg != Reg) { in loadImmediate()
402 if (DefReg!= SpReg) { in loadImmediate()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp704 Register DefReg; in collectInlineAsmInstrOperands() local
722 DefReg = MO.getReg(); in collectInlineAsmInstrOperands()
727 return DefReg; in collectInlineAsmInstrOperands()
788 Register DefReg = collectInlineAsmInstrOperands(I2); in insertInlineAsmProcess() local
789 if (!DefReg.isValid()) { in insertInlineAsmProcess()
790 DefReg = MRI.createGenericVirtualRegister(LLT::scalar(32)); in insertInlineAsmProcess()
791 MRI.setRegClass(DefReg, &SPIRV::iIDRegClass); in insertInlineAsmProcess()
795 GR->assignSPIRVTypeToVReg(VoidType, DefReg, MF); in insertInlineAsmProcess()
799 .addDef(DefReg) in insertInlineAsmProcess()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp684 const Register DefReg = MI.getOperand(0).getReg(); in select() local
685 const LLT DefTy = MRI->getType(DefReg); in select()
688 MRI->getRegClassOrRegBank(DefReg); in select()
707 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in select()
1108 Register DefReg = MI.getOperand(0).getReg(); in selectAddr() local
1109 const LLT DefTy = MRI->getType(DefReg); in selectAddr()
1135 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {}) in selectAddr()
1163 auto Result = MIB.buildInstr(RISCV::ADDI, {DefReg}, {AddrHiDest}) in selectAddr()
1189 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {}) in selectAddr()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp302 MachineInstr *emitADD(Register DefReg, MachineOperand &LHS,
2443 Register DefReg = I.getOperand(0).getReg(); in earlySelect() local
2444 LLT Ty = MRI.getType(DefReg); in earlySelect()
2447 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in earlySelect()
2450 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI); in earlySelect()
2593 const Register DefReg = I.getOperand(0).getReg(); in select() local
2594 const LLT DefTy = MRI.getType(DefReg); in select()
2597 MRI.getRegClassOrRegBank(DefReg); in select()
2616 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
2736 const Register DefReg = I.getOperand(0).getReg(); in select() local
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