| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 418 const TargetRegisterClass *DefRC, in shareSameRegisterFile() argument
426 if (DefRC == SrcRC && DefSubReg == SrcSubReg) in shareSameRegisterFile()
432 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
440 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
445 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
448 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
451 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
456 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
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| H A D | PeepholeOptimizer.cpp | 459 bool findNextSource(const TargetRegisterClass *DefRC, unsigned DefSubReg,
998 bool PeepholeOptimizer::findNextSource(const TargetRegisterClass *DefRC, in findNextSource() argument
1070 if (!TRI->shouldRewriteCopySrc(DefRC, DefSubReg, SrcRC, in findNextSource()
1189 const TargetRegisterClass *DefRC = MRI->getRegClass(Dst.Reg); in optimizeCoalescableCopyImpl() local
1195 if (!findNextSource(DefRC, Dst.SubReg, TrackPair, RewriteMap)) in optimizeCoalescableCopyImpl()
1276 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource() local
1277 Register NewVReg = MRI->createVirtualRegister(DefRC); in rewriteSource()
1334 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in optimizeUncoalescableCopy() local
1338 if (!findNextSource(DefRC, Def.SubReg, Def, RewriteMap)) in optimizeUncoalescableCopy()
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| H A D | DetectDeadLanes.cpp | 289 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes() local
303 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
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| H A D | RegisterCoalescer.cpp | 1377 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef() local
1388 if (!DefRC->contains(NewDstReg)) in reMaterializeTrivialDef()
1424 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1517 if (DefRC != nullptr) { in reMaterializeTrivialDef()
1519 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx); in reMaterializeTrivialDef()
1521 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 38 const TargetRegisterClass *DefRC = nullptr; member
50 FoldableDef(MachineOperand &FoldOp, const TargetRegisterClass *DefRC, in FoldableDef()
52 : DefRC(DefRC), DefSubReg(DefSubReg), Kind(FoldOp.getType()) { in FoldableDef()
66 FoldableDef(int64_t FoldImm, const TargetRegisterClass *DefRC, in FoldableDef()
68 : ImmToFold(FoldImm), DefRC(DefRC), DefSubReg(DefSubReg), in FoldableDef()
1123 FoldableDef FoldableImm(DefOp.getImm(), OpToFold.DefRC, in tryToFoldACImm()
1806 const TargetRegisterClass *DefRC = in foldCopyToAGPRRegSequence() local
1808 if (!TRI->isAGPRClass(DefRC)) in foldCopyToAGPRRegSequence()
1848 DefRC, &AMDGPU::AGPR_32RegClass, SubRegIdx); in foldCopyToAGPRRegSequence()
1868 TRI->getMatchingSuperRegClass(DefRC, InputRC, SubRegIdx); in foldCopyToAGPRRegSequence()
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| H A D | AMDGPUInstructionSelector.cpp | 305 const TargetRegisterClass *DefRC = in selectPHI() local
307 if (!DefRC) { in selectPHI()
314 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB); in selectPHI()
315 if (!DefRC) { in selectPHI()
337 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 162 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| H A D | ARMBaseRegisterInfo.cpp | 965 bool ARMBaseRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
970 if (DefRC == &ARM::SPRRegClass && DefSubReg == 0 && in shouldRewriteCopySrc()
975 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg, in shouldRewriteCopySrc()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 423 const TargetRegisterClass *DefRC = nullptr; in select() local
425 DefRC = TRI.getRegClass(DestReg); in select()
427 DefRC = getRegClassForTypeOnBank(DestReg, MRI); in select()
430 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 690 const TargetRegisterClass *DefRC = in select() local
692 if (!DefRC) { in select()
699 DefRC = getRegClassForTypeOnBank(DefTy, RB); in select()
700 if (!DefRC) { in select()
707 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in select()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 684 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 1956 auto *DefRC = MRI->getRegClass(OldDefReg); in hardenPostLoad() local
1961 Register UnhardenedReg = MRI->createVirtualRegister(DefRC); in hardenPostLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 1949 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); in evaluate() local
1950 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1951 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2599 const TargetRegisterClass *DefRC = in select() local
2601 if (!DefRC) { in select()
2607 DefRC = getRegClassForTypeOnBank(DefTy, RB); in select()
2608 if (!DefRC) { in select()
2616 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
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