| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 380 const TargetRegisterClass *DefRC, in shareSameRegisterFile() argument
385 if (DefRC == SrcRC) in shareSameRegisterFile()
391 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
399 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
404 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
407 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
410 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
415 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
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| H A D | DetectDeadLanes.cpp | 289 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes() local
303 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
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| H A D | PeepholeOptimizer.cpp | 731 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource() local
794 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
1293 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource() local
1294 Register NewVReg = MRI->createVirtualRegister(DefRC); in rewriteSource()
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| H A D | RegisterCoalescer.cpp | 1343 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef() local
1354 if (!DefRC->contains(NewDstReg)) in reMaterializeTrivialDef()
1390 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1482 if (DefRC != nullptr) { in reMaterializeTrivialDef()
1484 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx); in reMaterializeTrivialDef()
1486 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.h | 76 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| H A D | X86RegisterInfo.cpp | 221 bool X86RegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
228 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()
232 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg, in shouldRewriteCopySrc()
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| H A D | X86SpeculativeLoadHardening.cpp | 1959 auto *DefRC = MRI->getRegClass(OldDefReg); in hardenPostLoad() local
1964 Register UnhardenedReg = MRI->createVirtualRegister(DefRC); in hardenPostLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 423 const TargetRegisterClass *DefRC = nullptr; in select() local
425 DefRC = TRI.getRegClass(DestReg); in select()
427 DefRC = getRegClassForTypeOnBank(DestReg, MRI); in select()
430 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 936 bool ARMBaseRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
941 if (DefRC == &ARM::SPRRegClass && DefSubReg == 0 && in shouldRewriteCopySrc()
946 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg, in shouldRewriteCopySrc()
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| H A D | ARMBaseRegisterInfo.h | 237 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 526 const TargetRegisterClass *DefRC = in select() local
528 if (!DefRC) { in select()
535 DefRC = getRegClassForTypeOnBank(DefTy, RB); in select()
536 if (!DefRC) { in select()
543 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 270 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| H A D | AMDGPUInstructionSelector.cpp | 221 const TargetRegisterClass *DefRC in selectPHI() local
223 if (!DefRC) { in selectPHI()
230 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB); in selectPHI()
231 if (!DefRC) { in selectPHI()
239 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
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| H A D | SIRegisterInfo.cpp | 2926 const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
2946 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 658 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 1952 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); in evaluate() local
1953 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1954 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2470 const TargetRegisterClass *DefRC in select() local
2472 if (!DefRC) { in select()
2478 DefRC = getRegClassForTypeOnBank(DefTy, RB); in select()
2479 if (!DefRC) { in select()
2487 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
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