Searched refs:DS_WRITE (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUIGroupLP.cpp | 77 DS_WRITE = 1u << 9, enumerator
80 DS_READ | DS_WRITE | TRANS,
2208 SchedGroupMask::DS_WRITE, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
2240 SchedGroupMask::DS_WRITE, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
2265 SchedGroupMask::DS_WRITE, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
2279 SchedGroupMask::DS_WRITE, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
2433 else if (((SGMask & SchedGroupMask::DS_WRITE) != SchedGroupMask::NONE) && in canAddMI()
2643 InvertedMask &= ~SchedGroupMask::DS_READ & ~SchedGroupMask::DS_WRITE; in invertSchedBarrierMask()
2646 (InvertedMask & SchedGroupMask::DS_WRITE) == SchedGroupMask::NONE) in invertSchedBarrierMask()
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| H A D | SILoadStoreOptimizer.cpp | 75 DS_WRITE, enumerator
528 return DS_WRITE; in getInstClass()
782 case DS_WRITE: in setMI()
811 if ((InstClass == DS_READ) || (InstClass == DS_WRITE)) { in setMI()
1041 if ((CI.InstClass != DS_READ) && (CI.InstClass != DS_WRITE)) { in offsetsCanBeCombined()
1213 if (CI.InstClass == DS_READ || CI.InstClass == DS_WRITE) in checkAndPrepareMerge()
2291 if (CI.InstClass == DS_WRITE && CI.IsAGPR) { in collectMergeableInsts()
2409 case DS_WRITE: in optimizeInstsWithSameBaseAddr()
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