| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 73 const DebugLoc &DL, unsigned DReg,
87 const DebugLoc &DL, unsigned DReg,
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local
147 if (DReg != ARM::NoRegister) return ARM::ssub_1; in getDPRLaneFromSPR()
431 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
438 .addReg(DReg, 0, Lane); in createExtractSubreg()
476 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
482 .addReg(DReg) in createInsertSubreg()
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| H A D | ARMBaseInstrInfo.cpp | 5077 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane() local
5080 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
5081 return DReg; in getCorrespondingDRegAndLane()
5084 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5086 assert(DReg && "S-register with no D super-register?"); in getCorrespondingDRegAndLane()
5087 return DReg; in getCorrespondingDRegAndLane()
5106 MachineInstr &MI, unsigned DReg, in getImplicitSPRUseForDPRUse() argument
5110 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) { in getImplicitSPRUseForDPRUse()
5116 ImplicitSReg = TRI->getSubReg(DReg, in getImplicitSPRUseForDPRUse()
5134 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips16FrameLowering.cpp | 76 unsigned DReg = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
78 MCCFIInstruction::createOffset(nullptr, DReg, Offset)); in emitPrologue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 934 unsigned DReg = llvm::countr_zero(Defs); in adjustLiveRegs() local
935 LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg in adjustLiveRegs()
937 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); in adjustLiveRegs()
938 std::swap(RegMap[KReg], RegMap[DReg]); in adjustLiveRegs()
940 Defs &= ~(1 << DReg); in adjustLiveRegs()
966 unsigned DReg = llvm::countr_zero(Defs); in adjustLiveRegs() local
967 LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n"); in adjustLiveRegs()
969 pushReg(DReg); in adjustLiveRegs()
970 Defs &= ~(1 << DReg); in adjustLiveRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kBaseInfo.h | 106 DReg = 0x8, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4930 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotation() local
4933 unsigned TmpReg = DReg; in expandRotation()
4939 if (DReg == SReg) { in expandRotation()
4947 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4952 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4979 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4980 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4993 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotationImm() local
5006 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
5011 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 466 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency() local
473 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 945 unsigned DReg = CSKY::F0_64 + RegNo; in getRegForInlineAsmConstraint() local
948 return std::make_pair(DReg, &CSKY::sFPR64RegClass); in getRegForInlineAsmConstraint()
950 return std::make_pair(DReg, &CSKY::FPR64RegClass); in getRegForInlineAsmConstraint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.td | 177 def MxDRegClass : MxOpClass<"DReg">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 5936 unsigned DReg = RegNo - LoongArch::F0 + LoongArch::F0_64; in getRegForInlineAsmConstraint() local
5937 return std::make_pair(DReg, &LoongArch::FPR64RegClass); in getRegForInlineAsmConstraint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2505 void setVecListOneD(unsigned int DReg) { in setVecListOneD() argument
2507 VectorList.RegNum = DReg; in setVecListOneD()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 20788 unsigned DReg = RISCV::F0_D + RegNo; in getRegForInlineAsmConstraint() local
20789 return std::make_pair(DReg, &RISCV::FPR64RegClass); in getRegForInlineAsmConstraint()
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