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Searched refs:DQ (Results 1 – 25 of 26) sorted by relevance

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/freebsd/usr.sbin/jail/
H A Djaillex.l56 %start _ DQ
77 <_,DQ>[A-Za-z0-9_!%&()\-.:<>?@\[\]^`|~]+ |
78 <_,DQ>\\(.|\n|[0-7]{1,3}|x[0-9A-Fa-f]{1,2}) |
79 <_,DQ>[$*+/\\] {
105 BEGIN DQ; variable
110 <DQ>\" BEGIN _;
113 <_,DQ>$[A-Za-z_][A-Za-z_0-9]* {
118 <DQ>$\{([^\n\"{}]|\\(.|\n))*\} {
136 <DQ>$\{([^\n\"{}]|\\.)* {
/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt94 the PHY side DQ line (including DQS/DQ/DM line)
120 the PHY side DQ line (including DQS/DQ/DM line)
137 the DRAM side ODT on DQS/DQ line strength in ohms.
153 the PHY side DQ line (including DQS/DQ/DM line)
/freebsd/sys/contrib/device-tree/Bindings/power/supply/
H A Dmaxim,ds2760.txt17 sleep mode when the DQ line goes low for greater
18 than 2 seconds and leave sleep Mode when the DQ
/freebsd/crypto/openssl/test/
H A Drsa_sp800_56b_test.c281 const int DQ = 13; in test_check_crt_components() local
306 && TEST_BN_eq_word(key->dmq1, DQ) in test_check_crt_components()
320 && TEST_true(BN_set_word(key->dmq1, DQ)) in test_check_crt_components()
332 && TEST_true(BN_set_word(key->dmq1, DQ-1)) in test_check_crt_components()
334 && TEST_true(BN_set_word(key->dmq1, DQ)) in test_check_crt_components()
H A Dkeymgmt_internal_test.c76 #define DQ 7 macro
128 || !TEST_true(get_ulong_via_BN(p, &keydata[DQ])) in export_cb()
169 0xbd87, /* DQ */ in test_pass_rsa()
199 || !TEST_true(BN_set_word(bn2, expected[DQ])) in test_pass_rsa()
H A Devp_pkey_provided_test.c346 #define DQ 6 macro
367 0xbd87, /* DQ */ in test_fromdata_rsa()
377 OSSL_PARAM_ulong(OSSL_PKEY_PARAM_RSA_EXPONENT2, &key_numbers[DQ]), in test_fromdata_rsa()
/freebsd/contrib/llvm-project/clang/include/clang/Sema/
H A DSemaConcept.h239 bool subsumes(Sema &S, NamedDecl *DP, ArrayRef<const Expr *> P, NamedDecl *DQ, in subsumes() argument
253 getNormalizedAssociatedConstraints(S, DQ, Q); in subsumes()
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dcadence-nand-controller.txt22 + DQ PAD delay
/freebsd/contrib/sendmail/contrib/
H A Dmail.local.linux53 M*X)M>E<[!V81H,WC71:>&<$4/@\$_`2F&8.'.]T!L`B5_*(6DQ#,(!#!>$U4
156 M):D,KJ@5<`MR.0F]1;>DQ;[0$F2`3B`N,Z$F<(2<(`-L@&)@+F2QN4"7I2!=
164 MH#%?1LH(BPM)9';,F>DQ:P+(_`@A`R?>C!CBD7=BSNP)F`<2GTR>*19\IC?T
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCAsmStreamer.cpp953 const char DQ = '"'; in emitXCOFFRenameDirective() local
954 OS << ',' << DQ; in emitXCOFFRenameDirective()
957 if (C == DQ) in emitXCOFFRenameDirective()
958 OS << DQ; in emitXCOFFRenameDirective()
961 OS << DQ; in emitXCOFFRenameDirective()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td404 // DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
410 bits<12> DQ;
416 let Inst{16-27} = DQ;
427 bits<12> DQ;
432 let Inst{16-27} = DQ;
H A DPPCInstrP10.td853 bits<12> DQ;
860 let Inst{16-27} = DQ;
1157 (ins (memrix16 $DQ, $RA):$addr), "lxvp $XTp, $addr",
1166 (memrix16 $DQ, $RA):$addr), "stxvp $XTp, $addr",
H A DPPCInstr64Bit.td1454 (ins (memrix16 $DQ, $RA):$addr),
H A DPPCInstrVSX.td1671 def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins (memrix16 $DQ, $RA):$addr),
1709 def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, (memrix16 $DQ, $RA):$addr),
H A DPPCInstrInfo.td617 // as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form
676 // x-form addressing mode whose associated displacement form is DQ.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleZnver4.td193 // (v)FMUL*, (v)FMA*, Floating Point Compares, Blendv(DQ)
260 // (v)FMUL*, (v)FMA*, Floating Point Compares, Blendv(DQ)
1581 "(V?)P(SLL|SRL|SRA)(D|Q|W|DQ)(Y?|Z?|Z128?|Z256?)(rr|rrk|rrkz)",
1583 "(V?)P(SLL|SRL)DQ(Z?|Z256?)ri",
1649 "(V?)PMOV(SX|ZX)(BD|BQ|BW|WD|WQ|DQ)(Z128?|Z256?)(rr|rrk|rrkz)",
1651 "(V?)PMOV(SX|US|ZX)(DQ|WD|QW|WQ?)(Y|Z128?)(rr|rrk|rrkz)",
1661 "(V?)PMOV(SX|ZX)(BD|BQ|BW|WD|WQ|DQ)(Z?)(rr|rrk|rrkz)"
H A DX86SchedAlderlakeP.td693 def : InstRW<[ADLPWriteResGroup21], (instregex "^C(DQ|WD)E$",
702 def : InstRW<[ADLPWriteResGroup22], (instregex "^C(DQ|QO)$",
1347 def : InstRW<[ADLPWriteResGroup118], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>;
1353 def : InstRW<[ADLPWriteResGroup119], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
H A DX86MCInstLower.cpp2156 CASE_MOVX_RM(SX, DQ) in addConstantComments()
2175 CASE_MOVX_RM(ZX, DQ) in addConstantComments()
H A DX86SchedSkylakeServer.td448 defm : SKXWriteResPair<WriteCvtSS2I, [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
460 defm : SKXWriteResPair<WriteCvtI2PSZ, [SKXPort05], 4>; // Needs more work: DD vs DQ.
845 "KUNPCK(BW|DQ|WD)rr",
H A DX86SchedIceLake.td453 defm : ICXWriteResPair<WriteCvtSS2I, [ICXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
465 defm : ICXWriteResPair<WriteCvtI2PSZ, [ICXPort05], 4>; // Needs more work: DD vs DQ.
860 "KUNPCK(BW|DQ|WD)rr",
H A DX86ScheduleZnver3.td204 // (v)FMUL*, (v)FMA*, Floating Point Compares, Blendv(DQ)
271 // (v)FMUL*, (v)FMA*, Floating Point Compares, Blendv(DQ)
H A DX86SchedSapphireRapids.td772 def : InstRW<[SPRWriteResGroup23], (instregex "^C(DQ|WD)E$",
784 def : InstRW<[SPRWriteResGroup24], (instregex "^C(DQ|QO)$",
1325 "^KUNPCK(BW|DQ|WD)rr$")>;
1621 def : InstRW<[SPRWriteResGroup127], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>;
1627 def : InstRW<[SPRWriteResGroup128], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
H A DX86ScheduleZnver2.td1146 // CVT(T)P(D|S)2DQ.
H A DX86InstrSSE.td5048 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem, NoVLX>;
H A DX86InstrAVX512.td1296 // the unmasked patterns so that we only use the DQ instructions when masking

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