| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUImageIntrinsicOptimizer.cpp | 203 ConstantInt *DMask = cast<ConstantInt>( in optimizeSection() local
205 unsigned DMaskVal = DMask->getZExtValue() & 0xf; in optimizeSection()
242 ConstantInt::get(DMask->getType(), NewMaskVal); in optimizeSection()
|
| H A D | MIMGInstructions.td | 426 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
439 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
450 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
463 (ins SReg_256:$srsrc, DMask:$dmask,
475 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
488 (ins SReg_256:$srsrc, DMask:$dmask,
501 (ins SReg_256:$rsrc, DMask:$dmask, Dim:$dim,
515 (ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
532 (ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
684 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
[all …]
|
| H A D | SILoadStoreOptimizer.cpp | 115 unsigned DMask; member
182 return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset; in operator <()
798 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
948 unsigned MaxMask = std::max(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
949 unsigned MinMask = std::min(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
1440 unsigned MergedDMask = CI.DMask | Paired.DMask; in mergeImagePair()
1815 assert(((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == Width) && in getNewOpcode()
1825 ((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == in getSubRegIdxs()
|
| H A D | AMDGPUInstCombineIntrinsic.cpp | 1357 ConstantInt *DMask = cast<ConstantInt>(Args[DMaskIdx]); in simplifyAMDGCNMemoryIntrinsicDemanded() local
1358 unsigned DMaskVal = DMask->getZExtValue() & 0xf; in simplifyAMDGCNMemoryIntrinsicDemanded()
1379 Args[DMaskIdx] = ConstantInt::get(DMask->getType(), NewDMaskVal); in simplifyAMDGCNMemoryIntrinsicDemanded()
|
| H A D | AMDGPUInstructionSelector.cpp | 1843 unsigned DMask = 0; in selectImageIntrinsic() local
1859 DMask = Is64Bit ? 0xf : 0x3; in selectImageIntrinsic()
1862 DMask = Is64Bit ? 0x3 : 0x1; in selectImageIntrinsic()
1866 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in selectImageIntrinsic()
1867 DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); in selectImageIntrinsic()
2007 MIB.addImm(DMask); // dmask in selectImageIntrinsic()
|
| H A D | AMDGPULegalizerInfo.cpp | 6336 unsigned DMask = 0; in legalizeImageIntrinsic() local
6361 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in legalizeImageIntrinsic()
6364 } else if (DMask != 0) { in legalizeImageIntrinsic()
6365 DMaskLanes = llvm::popcount(DMask); in legalizeImageIntrinsic()
6392 if (IsTFE && DMask == 0) { in legalizeImageIntrinsic()
6393 DMask = 0x1; in legalizeImageIntrinsic()
6395 MI.getOperand(ArgOffset + Intr->DMaskIndex).setImm(DMask); in legalizeImageIntrinsic()
|
| H A D | SIISelLowering.cpp | 1223 unsigned DMask in getTgtMemIntrinsic() local
1225 MaxNumLanes = DMask == 0 ? 1 : llvm::popcount(DMask); in getTgtMemIntrinsic()
1244 unsigned DMask = cast<ConstantInt>(CI.getArgOperand(1))->getZExtValue(); in getTgtMemIntrinsic() local
1245 unsigned DMaskLanes = DMask == 0 ? 1 : llvm::popcount(DMask); in getTgtMemIntrinsic()
7923 unsigned DMask; in lowerImage() local
7942 DMask = Is64Bit ? 0xf : 0x3; in lowerImage()
7945 DMask = Is64Bit ? 0x3 : 0x1; in lowerImage()
7949 DMask = Op->getConstantOperandVal(ArgOffset + Intr->DMaskIndex); in lowerImage()
7950 DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); in lowerImage()
8133 DMask = 0x1; in lowerImage()
[all …]
|
| H A D | SIInstrInfo.cpp | 4874 const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask); in verifyInstruction() local
4875 if (DMask) { in verifyInstruction()
4876 uint64_t DMaskImm = DMask->getImm(); in verifyInstruction()
|
| H A D | SIInstrInfo.td | 1106 def DMask : NamedIntOperand<i16, "dmask">;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3879 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGDataSize() local
3880 if (DMask == 0) in validateMIMGDataSize()
3881 DMask = 1; in validateMIMGDataSize()
3885 (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask); in validateMIMGDataSize()
3986 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGAtomicDMask() local
3992 return DMask == 0x1 || DMask == 0x3 || DMask == 0xf; in validateMIMGAtomicDMask()
4004 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGGatherDMask() local
4011 return DMask == 0x1 || DMask == 0x2 || DMask == 0x4 || DMask == 0x8; in validateMIMGGatherDMask()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 1016 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; in convertMIMGInst() local
1017 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); in convertMIMGInst()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAMDGPU.td | 888 // Marker class for intrinsics with a DMask that determines the returned
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41437 int DMask[] = {0, 1, 2, 3}; in combineTargetShuffle() local
41439 DMask[DOffset + 0] = DOffset + 1; in combineTargetShuffle()
41440 DMask[DOffset + 1] = DOffset + 0; in combineTargetShuffle()
41444 getV4X86ShuffleImm8ForMask(DMask, DL, DAG)); in combineTargetShuffle()
41459 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D); in combineTargetShuffle() local
41470 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2; in combineTargetShuffle()
|