| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUImageIntrinsicOptimizer.cpp | 203 ConstantInt *DMask = cast<ConstantInt>( in optimizeSection() local
205 unsigned DMaskVal = DMask->getZExtValue() & 0xf; in optimizeSection()
241 ConstantInt::get(DMask->getType(), NewMaskVal); in optimizeSection()
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| H A D | MIMGInstructions.td | 428 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
441 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
452 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
465 (ins SReg_256_XNULL:$srsrc, DMask:$dmask,
477 let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
490 (ins SReg_256_XNULL:$srsrc, DMask:$dmask,
503 (ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
517 (ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
534 (ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
685 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
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| H A D | SILoadStoreOptimizer.cpp | 116 unsigned DMask; member
183 return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset; in operator <()
834 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
984 unsigned MaxMask = std::max(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
985 unsigned MinMask = std::min(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
1476 unsigned MergedDMask = CI.DMask | Paired.DMask; in mergeImagePair()
1876 assert(((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == Width) && in getNewOpcode()
1886 ((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == in getSubRegIdxs()
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| H A D | AMDGPUInstCombineIntrinsic.cpp | 1784 ConstantInt *DMask = cast<ConstantInt>(Args[DMaskIdx]); in simplifyAMDGCNMemoryIntrinsicDemanded() local
1785 unsigned DMaskVal = DMask->getZExtValue() & 0xf; in simplifyAMDGCNMemoryIntrinsicDemanded()
1806 Args[DMaskIdx] = ConstantInt::get(DMask->getType(), NewDMaskVal); in simplifyAMDGCNMemoryIntrinsicDemanded()
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| H A D | AMDGPULegalizerInfo.cpp | 6466 unsigned DMask = 0; in legalizeImageIntrinsic() local
6491 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in legalizeImageIntrinsic()
6494 } else if (DMask != 0) { in legalizeImageIntrinsic()
6495 DMaskLanes = llvm::popcount(DMask); in legalizeImageIntrinsic()
6522 if (IsTFE && DMask == 0) { in legalizeImageIntrinsic()
6523 DMask = 0x1; in legalizeImageIntrinsic()
6525 MI.getOperand(ArgOffset + Intr->DMaskIndex).setImm(DMask); in legalizeImageIntrinsic()
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| H A D | AMDGPUInstructionSelector.cpp | 2072 unsigned DMask = 0; in selectImageIntrinsic() local
2088 DMask = Is64Bit ? 0xf : 0x3; in selectImageIntrinsic()
2091 DMask = Is64Bit ? 0x3 : 0x1; in selectImageIntrinsic()
2095 DMask = MI.getOperand(ArgOffset + Intr->DMaskIndex).getImm(); in selectImageIntrinsic()
2096 DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); in selectImageIntrinsic()
2236 MIB.addImm(DMask); // dmask in selectImageIntrinsic()
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| H A D | SIISelLowering.cpp | 1295 unsigned DMask = in getTgtMemIntrinsic() local
1297 MaxNumLanes = DMask == 0 ? 1 : llvm::popcount(DMask); in getTgtMemIntrinsic()
1316 unsigned DMask = cast<ConstantInt>(CI.getArgOperand(1))->getZExtValue(); in getTgtMemIntrinsic() local
1317 unsigned DMaskLanes = DMask == 0 ? 1 : llvm::popcount(DMask); in getTgtMemIntrinsic()
8486 unsigned DMask; in lowerImage() local
8505 DMask = Is64Bit ? 0xf : 0x3; in lowerImage()
8508 DMask = Is64Bit ? 0x3 : 0x1; in lowerImage()
8512 DMask = Op->getConstantOperandVal(ArgOffset + Intr->DMaskIndex); in lowerImage()
8513 DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); in lowerImage()
8695 DMask = 0x1; in lowerImage()
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| H A D | SIInstrInfo.cpp | 5060 const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask); in verifyInstruction() local
5061 if (DMask) { in verifyInstruction()
5062 uint64_t DMaskImm = DMask->getImm(); in verifyInstruction()
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| H A D | SIInstrInfo.td | 1236 def DMask : NamedIntOperand<"dmask">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 4139 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGDataSize() local
4140 if (DMask == 0) in validateMIMGDataSize()
4141 DMask = 1; in validateMIMGDataSize()
4145 (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask); in validateMIMGDataSize()
4247 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGAtomicDMask() local
4253 return DMask == 0x1 || DMask == 0x3 || DMask == 0xf; in validateMIMGAtomicDMask()
4265 unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; in validateMIMGGatherDMask() local
4272 return DMask == 0x1 || DMask == 0x2 || DMask == 0x4 || DMask == 0x8; in validateMIMGGatherDMask()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 1241 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; in convertMIMGInst() local
1242 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); in convertMIMGInst()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAMDGPU.td | 1109 // Marker class for intrinsics with a DMask that determines the returned
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 43077 int DMask[] = {0, 1, 2, 3}; in combineTargetShuffle() local
43079 DMask[DOffset + 0] = DOffset + 1; in combineTargetShuffle()
43080 DMask[DOffset + 1] = DOffset + 0; in combineTargetShuffle()
43084 getV4X86ShuffleImm8ForMask(DMask, DL, DAG)); in combineTargetShuffle()
43099 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D); in combineTargetShuffle() local
43110 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2; in combineTargetShuffle()
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