Home
last modified time | relevance | path

Searched refs:DIVUW (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoM.td20 def riscv_divuw : SDNode<"RISCVISD::DIVUW", SDT_RISCVIntBinOpW>;
57 def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">,
89 def : PatGprGpr<riscv_divuw, DIVUW>;
93 // in fewer instructions than emitting DIVUW/REMUW then zero-extending the
128 def : PatGprGpr<udiv, DIVUW, i32, i32>;
H A DRISCVOptWInstrs.cpp156 case RISCV::DIVUW: in hasAllNBitUsers()
H A DRISCVISelLowering.h77 DIVUW, enumerator
H A DRISCVISelDAGToDAG.cpp3141 case RISCV::DIVUW: in hasAllNBitUsers()
H A DRISCVISelLowering.cpp12149 return RISCVISD::DIVUW; in getRISCVWOpcode()
12162 // SLLW/DIVUW/.../*W later one because the fact the operation was originally of in customLegalizeToWOp()
17855 case RISCVISD::DIVUW: { in computeKnownBitsForTargetNode()
17982 case RISCVISD::DIVUW: in ComputeNumSignBitsForTargetNode()
20399 NODE_NAME_CASE(DIVUW) in getTargetNodeName()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h168 R_TYPE_INST(DIVUW);
280 DIVUW, REMW, REMUW, LR_W, SC_W, AMOSWAP_W, AMOADD_W, AMOXOR_W, AMOAND_W,
H A DEmulateInstructionRISCV.cpp480 {"DIVUW", 0xFE00707F, 0x200503B, DecodeRType<DIVUW>},
1102 bool operator()(DIVUW inst) { in operator ()()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.td1231 let cx = 1 in defm DIVUW : RRNCm<"divu.w", 0x6F, I32, i32, udiv>;