Searched refs:DDst (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 469 MachineInstr *DDst = DDep.getSUnit()->getInstr(); in adjustSchedDependency() local
471 for (unsigned OpNum = 0; OpNum < DDst->getNumOperands(); OpNum++) { in adjustSchedDependency()
472 const MachineOperand &MO = DDst->getOperand(OpNum); in adjustSchedDependency()
483 InstrInfo.getOperandLatency(&InstrItins, *SrcInst, 0, *DDst, UseIdx); in adjustSchedDependency()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 5235 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; in setExecutionDomain() local
5236 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane); in setExecutionDomain()
5246 if (DSrc == DDst) { in setExecutionDomain()
5250 MIB.addReg(DDst, RegState::Define) in setExecutionDomain()
5251 .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI))) in setExecutionDomain()
5278 DDst); in setExecutionDomain()
5283 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain()
5287 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
5297 MIB.addReg(DDst, RegState::Define); in setExecutionDomain()
5301 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
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