Searched refs:DCLK_VOP0_DIV (Results 1 – 4 of 4) sorted by relevance
121 #define DCLK_VOP0_DIV 182 macro
200 GATE(DCLK_VOP0_DIV, "dclk_vop0_div", "dclk_vop0_div_c", 10, 12),
672 assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>,675 assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
131 #define DCLK_VOP0_DIV 182 macro