| /freebsd/sys/contrib/device-tree/src/arm/microchip/ |
| H A D | lan966x-kontron-kswitch-d10-mmt-8g.dts | 3 * Device Tree file for the Kontron KSwitch D10 MMT 8G
10 model = "Kontron KSwitch D10 MMT 8G";
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| H A D | lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 3 * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS
10 model = "Kontron KSwitch D10 MMT 6G-2GS";
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| H A D | lan966x-kontron-kswitch-d10-mmt.dtsi | 3 * Common part of the device tree for the Kontron KSwitch D10 MMT
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| /freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cli_root/zpool_scrub/ |
| H A D | zpool_scrub_print_repairing.ksh | 56 log_must zinject -d $DISK1 -D10:1 $TESTPOOL
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| /freebsd/lib/msun/ld128/ |
| H A D | s_expl.c | 180 D10 = 2.75573192239853161148064676533754048e-7L, variable
250 x * (D7 + x * (D8 + x * (D9 + x * (D10 + in expm1l()
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| /freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/events/ |
| H A D | zed_slow_io_many_vdevs.ksh | 84 log_must zinject -d $vdev -D10:1 $TESTPOOL
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| H A D | zed_slow_io.ksh | 98 log_must zinject -d $VDEV -D10:1 -T read $TESTPOOL
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 106 case D11: case D10: case D9: case D8: in isARMArea3Register()
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| H A D | ARMRegisterInfo.td | 131 def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
164 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
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| H A D | ARMCallingConv.td | 115 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 99 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, in getCalleeSavedSpillSlots()
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| H A D | HexagonRegisterInfo.td | 147 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
549 (add D11, D10, D9, D8, D3, D2, D1, D0)>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 141 case AArch64::D10: return AArch64::B10; in getBRegFromDReg()
181 case AArch64::B10: return AArch64::D10; in getDRegFromBReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 220 def D10 : Rd<20, "f20", [F20, F21]>, DwarfRegNum<[82]>;
286 def Q5 : Rq<20, "f20", [D10, D11]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 110 case AArch64::D10: in isOdd()
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| H A D | AArch64CallingConvention.td | 560 D8, D9, D10, D11,
572 D8, D9, D10, D11,
681 D8, D9, D10, D11,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 606 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, in DecodeDoubleRegsRegisterClass()
618 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; in DecodeGeneralDoubleLow8RegsRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 86 SP::D10, SP::D26, SP::D11, SP::D27,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 726 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
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| H A D | AArch64MCTargetDesc.cpp | 183 {codeview::RegisterId::ARM64_D10, AArch64::D10}, in initLLVMToCVRegMapping()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 290 {codeview::RegisterId::ARM_ND10, ARM::D10}, in initLLVMToCVRegMapping()
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| H A D | ARMAsmBackend.cpp | 1311 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; in generateCompactUnwindEncoding()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCDuplexInfo.cpp | 686 case Hexagon::D10: in addOps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterInfo.td | 411 D10, D11, D12, D13, D14, D15)>;
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| /freebsd/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am625-beagleplay.dts | 505 AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */
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