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Searched refs:Cycle (Results 1 – 25 of 42) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DGenericCycleImpl.h164 auto Cycle = BlockMapTopLevel.find(Block);
165 if (Cycle != BlockMapTopLevel.end())
166 return Cycle->second;
203 void GenericCycleInfo<ContextT>::addBlockToCycle(BlockT *Block, CycleT *Cycle) { in addBlockToCycle() argument
207 Cycle->appendBlock(Block); in addBlockToCycle()
208 BlockMap.try_emplace(Block, Cycle); in addBlockToCycle()
210 CycleT *ParentCycle = Cycle->getParentCycle(); in addBlockToCycle()
212 Cycle = ParentCycle; in addBlockToCycle()
213 Cycle->appendBlock(Block); in addBlockToCycle()
214 ParentCycle = Cycle->getParentCycle(); in addBlockToCycle()
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H A DGenericUniformityImpl.h131 void computeCyclePO(const CycleInfoT &CI, const CycleT *Cycle,
135 const CycleInfoT &CI, const CycleT *Cycle,
703 for (const auto *Cycle = CI.getCycle(&DivTermBlock); Cycle; in computeJoinPoints() local
704 Cycle = Cycle->getParentCycle()) { in computeJoinPoints()
705 if (Cycle->isReducible()) { in computeJoinPoints()
711 Cycle->getExitBlocks(Exits); in computeJoinPoints()
712 auto *Header = Cycle->getHeader(); in computeJoinPoints()
940 static const CycleT *getExtDivCycle(const CycleT *Cycle, in getExtDivCycle() argument
943 assert(Cycle); in getExtDivCycle()
944 assert(Cycle->contains(JoinBlock)); in getExtDivCycle()
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H A DGenericCycleInfo.h259 void addBlockToCycle(BlockT *Block, CycleT *Cycle);
285 Printable print(const CycleT *Cycle) { return Cycle->print(Context); } in print() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td461 // 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
524 // Three Cycle PM operation. Only one PM unit per superslice so we use the whole
634 // 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
658 // 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
666 // 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
683 // 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
691 // 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
700 // 76 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
709 // 6 Cycle Load uses a single slice.
715 // 5 Cycle Load uses a single slice.
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h91 DenseMap<MachineInstr *, int> Cycle; variable
109 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
111 : Loop(Loop), ScheduledInstrs(ScheduledInstrs), Cycle(std::move(Cycle)), in ModuloSchedule()
128 int getFirstCycle() { return Cycle[ScheduledInstrs.front()]; } in getFirstCycle()
132 int getFinalCycle() { return Cycle[ScheduledInstrs.back()]; } in getFinalCycle()
142 auto I = Cycle.find(MI); in getCycle()
143 return I == Cycle.end() ? -1 : I->second; in getCycle()
H A DMachineCycleAnalysis.h1 //===- MachineCycleAnalysis.h - Cycle Info for Machine IR -------*- C++ -*-===//
47 bool isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I);
H A DMachinePipeliner.h481 void reserveResources(const MCSchedClassDesc *SCDesc, int Cycle);
483 void unreserveResources(const MCSchedClassDesc *SCDesc, int Cycle);
519 bool canReserveResources(SUnit &SU, int Cycle);
523 void reserveResources(SUnit &SU, int Cycle);
H A DScheduleDAG.h563 void setCurCycle(unsigned Cycle) { in setCurCycle() argument
564 CurCycle = Cycle; in setCurCycle()
H A DMachineTraceMetrics.h76 unsigned Cycle = 0; member
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineTraceMetrics.cpp805 unsigned Cycle = 0; in updateDepth() local
818 Cycle = std::max(Cycle, DepCycle); in updateDepth()
822 MICycles.Depth = Cycle; in updateDepth()
826 TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Height); in updateDepth()
827 LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI); in updateDepth()
829 LLVM_DEBUG(dbgs() << Cycle << '\t' << UseMI); in updateDepth()
928 unsigned DepHeight = I->Cycle; in updatePhysDepsUpwards()
947 if (LRU.Cycle <= Height && LRU.MI != &MI) { in updatePhysDepsUpwards()
948 LRU.Cycle = Height; in updatePhysDepsUpwards()
1046 RegUnits[LI.Reg].Cycle = LI.Height; in computeInstrHeights()
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H A DMachineCycleAnalysis.cpp94 bool llvm::isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I) { in isCycleInvariant() argument
128 } else if (any_of(Cycle->getEntries(), in isCycleInvariant()
145 if (Cycle->contains(MRI->getVRegDef(Reg)->getParent())) in isCycleInvariant()
H A DWindowScheduler.cpp545 int Cycle = getOriCycle(SuccMI); in schedulePhi() local
547 LateCycle = std::min(LateCycle, Cycle); in schedulePhi()
583 for (int Cycle = 0; Cycle < (int)II; ++Cycle) { in getIssueOrder() local
584 if (!CycleToMIs.count(Cycle)) in getIssueOrder()
586 for (auto *MI : CycleToMIs[Cycle]) in getIssueOrder()
H A DMachinePipeliner.cpp707 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in schedule() local
708 ++Cycle) { in schedule()
709 for (SUnit *SU : Schedule.getInstructions(Cycle)) { in schedule()
711 Cycles[SU->getInstr()] = Cycle; in schedule()
1090 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in computeScheduledInsts() local
1091 ++Cycle) { in computeScheduledInsts()
1095 Cycle + Stage * Schedule.getInitiationInterval()))) { in computeScheduledInsts()
1096 Instrs[Cycle].push_front(SU); in computeScheduledInsts()
1101 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in computeScheduledInsts() local
1102 ++Cycle) { in computeScheduledInsts()
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H A DMachineSink.cpp254 void FindCycleSinkCandidates(MachineCycle *Cycle, MachineBasicBlock *BB,
256 bool SinkIntoCycle(MachineCycle *Cycle, MachineInstr &I);
676 MachineCycle *Cycle, MachineBasicBlock *BB, in FindCycleSinkCandidates() argument
685 if (!isCycleInvariant(Cycle, MI)) { in FindCycleSinkCandidates()
771 for (auto *Cycle : Cycles) { in runOnMachineFunction() local
772 MachineBasicBlock *Preheader = Cycle->getCyclePreheader(); in runOnMachineFunction()
778 FindCycleSinkCandidates(Cycle, Preheader, Candidates); in runOnMachineFunction()
791 if (!SinkIntoCycle(Cycle, *I)) in runOnMachineFunction()
1167 MachineCycle *Cycle = CI->getCycle(DefMI->getParent()); in isProfitableToSinkTo() local
1172 if (Cycle != MCycle || (DefMI->isPHI() && Cycle && Cycle->isReducible() && in isProfitableToSinkTo()
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/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DASTImporter.h169 using Cycle = llvm::iterator_range<VecTy::const_reverse_iterator>; variable
170 Cycle getCycleAtBack() const { in getCycleAtBack()
172 return Cycle(Nodes.rbegin(), in getCycleAtBack()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DUniformityAnalysis.cpp68 const Instruction &I, const Cycle &DefCycle) const { in usesValueFromCycle()
82 const Cycle &DefCycle) { in propagateTemporalDivergence()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DCycleInfo.h1 //===- CycleInfo.h - Cycle Info for LLVM IR -----------------*- C++ -*-===//
24 using Cycle = CycleInfo::CycleT;
27 using Cycle = CycleInfo::CycleT; global() variable
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dpwm-regulator.txt33 - voltage-table: Voltage and Duty-Cycle table consisting of 2 cells
85 /* Voltage Duty-Cycle */
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp596 bool findCycle(Value *Out, Value *In, ValueSeq &Cycle);
597 void classifyCycle(Instruction *DivI, ValueSeq &Cycle, ValueSeq &Early,
1126 ValueSeq &Cycle) { in findCycle() argument
1147 if (!Cycle.insert(I)) in findCycle()
1149 if (findCycle(I, In, Cycle)) in findCycle()
1151 Cycle.remove(I); in findCycle()
1153 return !Cycle.empty(); in findCycle()
1157 ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) { in classifyCycle() argument
1163 unsigned I, N = Cycle.size(); in classifyCycle()
1165 Value *V = Cycle[I]; in classifyCycle()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DCycleAnalysis.h1 //===- CycleAnalysis.h - Cycle Info for LLVM IR -----------------*- C++ -*-===//
28 using Cycle = CycleInfo::CycleT; global() variable
/freebsd/crypto/openssl/doc/life-cycles/
H A DREADME.md1 Algorithm Life-Cycle Diagrams
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h398 bool contains(unsigned Cycle) const { return Cycle >= Begin && Cycle < End; } in contains() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp438 unsigned Cycle = getTransSwizzle(TransSwz, i); in isLegalUpTo() local
443 if (Vector[Src.second][Cycle] < 0) in isLegalUpTo()
444 Vector[Src.second][Cycle] = Src.first; in isLegalUpTo()
445 if (Vector[Src.second][Cycle] != Src.first) in isLegalUpTo()
499 unsigned Cycle = getTransSwizzle(TransSwz, i); in isConstCompatible() local
502 if (ConstCount > 0 && Cycle == 0) in isConstCompatible()
504 if (ConstCount > 1 && Cycle == 1) in isConstCompatible()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h62 void notifyExecuted(unsigned Cycle);
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-s4-s805x2-aq222.dts93 /* Voltage Duty-Cycle */

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