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Searched refs:Cycle (Results 1 – 25 of 48) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DGenericUniformityImpl.h134 void computeCyclePO(const CycleInfoT &CI, const CycleT *Cycle,
138 const CycleInfoT &CI, const CycleT *Cycle,
719 for (const auto *Cycle = CI.getCycle(&DivTermBlock); Cycle; in computeJoinPoints() local
720 Cycle = Cycle->getParentCycle()) { in computeJoinPoints()
721 if (Cycle->isReducible()) { in computeJoinPoints()
727 Cycle->getExitBlocks(Exits); in computeJoinPoints()
728 auto *Header = Cycle->getHeader(); in computeJoinPoints()
956 static const CycleT *getExtDivCycle(const CycleT *Cycle, in getExtDivCycle() argument
959 assert(Cycle); in getExtDivCycle()
960 assert(Cycle->contains(JoinBlock)); in getExtDivCycle()
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H A DGenericCycleImpl.h271 auto Cycle = BlockMapTopLevel.find(Block);
272 if (Cycle != BlockMapTopLevel.end())
273 return Cycle->second;
312 void GenericCycleInfo<ContextT>::addBlockToCycle(BlockT *Block, CycleT *Cycle) { in addBlockToCycle() argument
316 Cycle->appendBlock(Block); in addBlockToCycle()
317 BlockMap.try_emplace(Block, Cycle); in addBlockToCycle()
319 CycleT *ParentCycle = Cycle->getParentCycle(); in addBlockToCycle()
321 Cycle = ParentCycle; in addBlockToCycle()
322 Cycle->appendBlock(Block); in addBlockToCycle()
323 ParentCycle = Cycle->getParentCycle(); in addBlockToCycle()
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H A DGenericCycleInfo.h308 void addBlockToCycle(BlockT *Block, CycleT *Cycle);
316 Printable print(const CycleT *Cycle) { return Cycle->print(Context); } in print() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td462 // 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
525 // Three Cycle PM operation. Only one PM unit per superslice so we use the whole
635 // 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
659 // 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
667 // 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
684 // 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
692 // 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
701 // 76 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
710 // 6 Cycle Load uses a single slice.
716 // 5 Cycle Load uses a single slice.
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineTraceMetrics.cpp833 unsigned Cycle = 0; in updateDepth() local
846 Cycle = std::max(Cycle, DepCycle); in updateDepth()
850 MICycles.Depth = Cycle; in updateDepth()
854 TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Height); in updateDepth()
855 LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI); in updateDepth()
857 LLVM_DEBUG(dbgs() << Cycle << '\t' << UseMI); in updateDepth()
956 unsigned DepHeight = I->Cycle; in updatePhysDepsUpwards()
975 if (LRU.Cycle <= Height && LRU.MI != &MI) { in updatePhysDepsUpwards()
976 LRU.Cycle = Height; in updatePhysDepsUpwards()
1074 RegUnits[LI.Reg.id()].Cycle = LI.Height; in computeInstrHeights()
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H A DMachineCycleAnalysis.cpp112 bool llvm::isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I) { in isCycleInvariant() argument
146 } else if (any_of(Cycle->getEntries(), in isCycleInvariant()
163 if (Cycle->contains(MRI->getVRegDef(Reg)->getParent())) in isCycleInvariant()
H A DMachinePipeliner.cpp853 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in schedule() local
854 ++Cycle) { in schedule()
855 for (SUnit *SU : Schedule.getInstructions(Cycle)) { in schedule()
857 Cycles[SU->getInstr()] = Cycle; in schedule()
1344 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in computeScheduledInsts() local
1345 ++Cycle) { in computeScheduledInsts()
1349 Cycle + Stage * Schedule.getInitiationInterval()))) { in computeScheduledInsts()
1350 Instrs[Cycle].push_front(SU); in computeScheduledInsts()
1355 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in computeScheduledInsts() local
1356 ++Cycle) { in computeScheduledInsts()
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H A DWindowScheduler.cpp545 int Cycle = getOriCycle(SuccMI); in schedulePhi() local
547 LateCycle = std::min(LateCycle, Cycle); in schedulePhi()
583 for (int Cycle = 0; Cycle < (int)II; ++Cycle) { in getIssueOrder() local
584 auto It = CycleToMIs.find(Cycle); in getIssueOrder()
H A DMachineSink.cpp261 void FindCycleSinkCandidates(MachineCycle *Cycle, MachineBasicBlock *BB,
265 aggressivelySinkIntoCycle(MachineCycle *Cycle, MachineInstr &I,
716 MachineCycle *Cycle, MachineBasicBlock *BB, in FindCycleSinkCandidates() argument
729 if (!isCycleInvariant(Cycle, MI)) { in FindCycleSinkCandidates()
888 for (auto *Cycle : Cycles) { in run() local
889 MachineBasicBlock *Preheader = Cycle->getCyclePreheader(); in run()
895 FindCycleSinkCandidates(Cycle, Preheader, Candidates); in run()
922 if (!aggressivelySinkIntoCycle(Cycle, *I, SunkInstrs)) in run()
1334 MachineCycle *Cycle = CI->getCycle(DefMI->getParent()); in isProfitableToSinkTo() local
1339 if (Cycle != MCycle || (DefMI->isPHI() && Cycle && Cycle->isReducible() && in isProfitableToSinkTo()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h91 DenseMap<MachineInstr *, int> Cycle; variable
109 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
111 : Loop(Loop), ScheduledInstrs(ScheduledInstrs), Cycle(std::move(Cycle)), in ModuloSchedule()
128 int getFirstCycle() { return Cycle[ScheduledInstrs.front()]; } in getFirstCycle()
132 int getFinalCycle() { return Cycle[ScheduledInstrs.back()]; } in getFinalCycle()
142 auto I = Cycle.find(MI); in getCycle()
143 return I == Cycle.end() ? -1 : I->second; in getCycle()
H A DMachineCycleAnalysis.h49 LLVM_ABI bool isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I);
H A DMachinePipeliner.h669 void reserveResources(const MCSchedClassDesc *SCDesc, int Cycle);
671 void unreserveResources(const MCSchedClassDesc *SCDesc, int Cycle);
707 bool canReserveResources(SUnit &SU, int Cycle);
711 void reserveResources(SUnit &SU, int Cycle);
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DFixIrreducible.cpp174 static void updateLoopInfo(LoopInfo &LI, Cycle &C, in updateLoopInfo()
228 static bool fixIrreducible(Cycle &C, CycleInfo &CI, DominatorTree &DT, in fixIrreducible()
316 if (Cycle *Parent = C.getParentCycle()) in fixIrreducible()
331 for (Cycle *TopCycle : CI.toplevel_cycles()) { in FixIrreducibleImpl()
332 for (Cycle *C : depth_first(TopCycle)) { in FixIrreducibleImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUGlobalISelDivergenceLowering.cpp252 const MachineCycle *Cycle = CycleMergedMask.first; in lowerTemporalDivergenceI1() local
260 for (auto Entry : Cycle->getEntries()) { in lowerTemporalDivergenceI1()
262 if (!Cycle->contains(Pred)) { in lowerTemporalDivergenceI1()
276 for (auto [Reg, UseInst, Cycle] : MUI->getTemporalDivergenceList()) { in lowerTemporalDivergenceI1()
H A DR600InstrInfo.cpp428 unsigned Cycle = getTransSwizzle(TransSwz, i); in isLegalUpTo() local
433 if (Vector[Src.second][Cycle] < 0) in isLegalUpTo()
434 Vector[Src.second][Cycle] = Src.first; in isLegalUpTo()
435 if (Vector[Src.second][Cycle] != Src.first) in isLegalUpTo()
489 unsigned Cycle = getTransSwizzle(TransSwz, i); in isConstCompatible() local
492 if (ConstCount > 0 && Cycle == 0) in isConstCompatible()
494 if (ConstCount > 1 && Cycle == 1) in isConstCompatible()
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DASTImporter.h170 using Cycle = llvm::iterator_range<VecTy::const_reverse_iterator>; variable
171 Cycle getCycleAtBack() const { in getCycleAtBack()
173 return Cycle(Nodes.rbegin(), in getCycleAtBack()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DUniformityAnalysis.cpp67 const Instruction &I, const Cycle &DefCycle) const { in usesValueFromCycle()
81 const Cycle &DefCycle) { in propagateTemporalDivergence()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DCycleInfo.h1 //===- CycleInfo.h - Cycle Info for LLVM IR -----------------*- C++ -*-===//
24 using Cycle = CycleInfo::CycleT;
27 using Cycle = CycleInfo::CycleT; global() variable
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dpwm-regulator.txt33 - voltage-table: Voltage and Duty-Cycle table consisting of 2 cells
85 /* Voltage Duty-Cycle */
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp586 bool findCycle(Value *Out, Value *In, ValueSeq &Cycle);
587 void classifyCycle(Instruction *DivI, ValueSeq &Cycle, ValueSeq &Early,
1113 ValueSeq &Cycle) { in findCycle() argument
1134 if (!Cycle.insert(I)) in findCycle()
1136 if (findCycle(I, In, Cycle)) in findCycle()
1138 Cycle.remove(I); in findCycle()
1140 return !Cycle.empty(); in findCycle()
1144 ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) { in classifyCycle() argument
1150 unsigned I, N = Cycle.size(); in classifyCycle()
1152 Value *V = Cycle[I]; in classifyCycle()
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/freebsd/crypto/openssl/doc/life-cycles/
H A DREADME.md1 Algorithm Life-Cycle Diagrams
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h399 bool contains(unsigned Cycle) const { return Cycle >= Begin && Cycle < End; } in contains() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaRegisterInfo.td190 // Cycle number to interrupt register 0
193 // Cycle number to interrupt register 1
196 // Cycle number to interrupt register 2
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h62 void notifyExecuted(unsigned Cycle);
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-s4-s805x2-aq222.dts93 /* Voltage Duty-Cycle */

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