Searched refs:CvtSrc (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPostLegalizerCombiner.cpp | 350 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local
354 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN()
358 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
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| H A D | AMDGPUISelLowering.cpp | 4896 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local
4897 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine()
4900 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine()
4908 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
4912 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local
4914 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine()
4917 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine()
4924 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 16400 SDValue CvtSrc = N1.getOperand(0); in visitFSUBForFMACombine() local
16401 SDValue N100 = CvtSrc.getOperand(0); in visitFSUBForFMACombine()
16402 SDValue N101 = CvtSrc.getOperand(1); in visitFSUBForFMACombine()
16403 SDValue N102 = CvtSrc.getOperand(2); in visitFSUBForFMACombine()
16406 CvtSrc.getValueType())) { in visitFSUBForFMACombine()
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