| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegNumbering.cpp | 90 unsigned CurReg = MFI.getParams().size(); in runOnMachineFunction() local
104 LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " << CurReg << "\n"); in runOnMachineFunction()
105 MFI.setWAReg(VReg, CurReg++); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 79 Register CurReg) override;
165 Register DstReg, Register PrevReg, Register CurReg) { in buildMergeLaneMasks() argument
170 Register CurRegCopy = buildRegCopyToLaneMask(CurReg); in buildMergeLaneMasks()
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| H A D | SILowerI1Copies.cpp | 80 Register CurReg) override;
857 Register CurReg) { in buildMergeLaneMasks() argument
861 bool CurConstant = isConstantLaneMask(CurReg, CurVal); in buildMergeLaneMasks()
865 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg); in buildMergeLaneMasks()
891 CurMaskedReg = CurReg; in buildMergeLaneMasks()
895 .addReg(CurReg) in buildMergeLaneMasks()
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| H A D | SILowerI1Copies.h | 94 Register PrevReg, Register CurReg) = 0;
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| H A D | SIInstrInfo.cpp | 6289 Register CurReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in emitLoadScalarOpsFromVGPRLoop() local
6291 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), CurReg) in emitLoadScalarOpsFromVGPRLoop()
6297 .addReg(CurReg) in emitLoadScalarOpsFromVGPRLoop()
6312 ScalarOp->setReg(CurReg); in emitLoadScalarOpsFromVGPRLoop()
6336 Register CurReg = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass); in emitLoadScalarOpsFromVGPRLoop() local
6337 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), CurReg) in emitLoadScalarOpsFromVGPRLoop()
6346 .addReg(CurReg); in emitLoadScalarOpsFromVGPRLoop()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86DomainReassignment.cpp | 548 unsigned CurReg = Worklist.pop_back_val(); in buildClosure() local
551 if (!C.insertEdge(CurReg)) in buildClosure()
555 MachineInstr *DefMI = MRI->getVRegDef(CurReg); in buildClosure()
579 for (auto &UseMI : MRI->use_nodbg_instructions(CurReg)) { in buildClosure()
582 if (usedAsAddr(UseMI, CurReg, TII)) { in buildClosure()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2580 unsigned CurReg = RegClass->getRegister(CurRegEnc); in tryFoldSPUpdateIntoPushPop() local
2587 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, in tryFoldSPUpdateIntoPushPop()
2597 if (isCalleeSavedRegister(CurReg, CSRegs) || in tryFoldSPUpdateIntoPushPop()
2598 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) != in tryFoldSPUpdateIntoPushPop()
2609 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, in tryFoldSPUpdateIntoPushPop()
5283 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain() local
5284 bool CurUndef = !MI.readsRegister(CurReg, TRI); in setExecutionDomain()
5285 NewMIB.addReg(CurReg, getUndefRegState(CurUndef)); in setExecutionDomain()
5287 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
5288 CurUndef = !MI.readsRegister(CurReg, TRI); in setExecutionDomain()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 9870 Register CurReg = Reg; in getIndVarInfo() local
9872 MachineInstr *Def = MRI.getVRegDef(CurReg); in getIndVarInfo()
9879 CurReg = Def->getOperand(1).getReg(); in getIndVarInfo()
9885 extractPhiReg(*Def, LoopBB, CurReg, InitReg); in getIndVarInfo()
9920 CurReg = Def->getOperand(UpdateCounterOprNum).getReg(); in getIndVarInfo()
9923 if (!CurReg.isVirtual()) in getIndVarInfo()
9925 if (Reg == CurReg) in getIndVarInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 11164 unsigned CurReg = 0; in LowerCallTo() local
11172 CLI.DAG, CLI.DL, &InVals[CurReg], NumRegs, RegisterVT, VT, nullptr, in LowerCallTo()
11174 CurReg += NumRegs; in LowerCallTo()
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