Searched refs:CopyOpc (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 262 int CopyOpc = 0; in emitThumbRegPlusImmediate()
275 // * CopyOpc - DestReg = BaseReg + imm in emitThumbRegPlusImmediate()
290 CopyOpc = ARM::tMOVr; in emitThumbRegPlusImmediate()
300 CopyOpc = ARM::tADDrSPi; in emitThumbRegPlusImmediate()
308 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3; in emitThumbRegPlusImmediate()
313 CopyOpc = ARM::tMOVr; in emitThumbRegPlusImmediate()
325 CopyOpc = ARM::tMOVr; in emitThumbRegPlusImmediate()
338 if (CopyOpc && Bytes < CopyScale) { in emitThumbRegPlusImmediate()
339 CopyOpc = ARM::tMOVr;
345 unsigned RequiredCopyInstrs = CopyOpc in removeOperands()
198 int CopyOpc = 0; emitThumbRegPlusImmediate() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyCFGStackify.cpp | 834 unsigned CopyOpc = in unstackifyVRegsUsedInSplitBB() local
836 BuildMI(MBB, &MI, MI.getDebugLoc(), TII.get(CopyOpc), TeeReg) in unstackifyVRegsUsedInSplitBB()
838 BuildMI(MBB, &MI, MI.getDebugLoc(), TII.get(CopyOpc), Reg).addReg(DefReg); in unstackifyVRegsUsedInSplitBB()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 2466 unsigned CopyOpc = TargetOpcode::COPY; in optimizeSpillSlots() local
2468 CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth; in optimizeSpillSlots()
2470 CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth; in optimizeSpillSlots()
2471 CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR) in optimizeSpillSlots()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 1966 unsigned CopyOpc = AMDGPU::COPY; in tryFoldPhiAGPR() local
1989 CopyOpc = AMDGPU::V_ACCVGPR_WRITE_B32_e64; in tryFoldPhiAGPR()
2001 TII->get(CopyOpc), NewReg) in tryFoldPhiAGPR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3854 static bool getLaneCopyOpcode(unsigned &CopyOpc, unsigned &ExtractSubReg, in getLaneCopyOpcode() argument
3860 CopyOpc = AArch64::DUPi8; in getLaneCopyOpcode()
3864 CopyOpc = AArch64::DUPi16; in getLaneCopyOpcode()
3868 CopyOpc = AArch64::DUPi32; in getLaneCopyOpcode()
3872 CopyOpc = AArch64::DUPi64; in getLaneCopyOpcode()
3887 unsigned CopyOpc = 0; in emitExtractVectorElt() local
3889 if (!getLaneCopyOpcode(CopyOpc, ExtractSubReg, ScalarTy.getSizeInBits())) { in emitExtractVectorElt()
3935 MIRBuilder.buildInstr(CopyOpc, {*DstReg}, {InsertReg}).addImm(LaneIdx); in emitExtractVectorElt()
4042 unsigned CopyOpc = 0; in selectUnmergeValues() local
4044 if (!getLaneCopyOpcode(CopyOpc, ExtractSubReg, NarrowTy.getSizeInBits())) in selectUnmergeValues()
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