| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 84 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
121 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
443 case ISD::CopyFromReg: in SUSchedulingCost()
548 case ISD::CopyFromReg: in initNumRegDefsLeft()
|
| H A D | StatepointLowering.cpp | 351 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
1201 SDValue CopyFromReg = getCopyFromRegs(SI, RetTy); in visitGCResult() local
1203 assert(CopyFromReg.getNode()); in visitGCResult()
1204 setValue(&CI, CopyFromReg); in visitGCResult()
|
| H A D | ScheduleDAGRRList.cpp | 324 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
713 case ISD::CopyFromReg: in EmitNode()
1276 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2281 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2381 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2452 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2469 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
3016 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
|
| H A D | InstrEmitter.cpp | 378 Op.getNode()->getOpcode() != ISD::CopyFromReg && !IsDebug && in AddRegisterOperand()
1173 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
1276 case ISD::CopyFromReg: { in EmitSpecialNode()
|
| H A D | ScheduleDAGSDNodes.cpp | 127 if (Def->getOpcode() == ISD::CopyFromReg && in CheckForPhysRegDependency()
555 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
|
| H A D | ScheduleDAGFast.cpp | 420 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
|
| H A D | SelectionDAGDumper.cpp | 184 case ISD::CopyFromReg: return "CopyFromReg"; in getOperationName()
|
| H A D | SelectionDAGBuilder.cpp | 5950 case ISD::CopyFromReg: { in getUnderlyingArgRegs()
10601 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) in visitPatchpoint()
11226 assert((Op.getOpcode() != ISD::CopyFromReg || in CopyValueToVirtualRegister()
11768 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { in LowerArguments()
11777 if (Res.getOpcode() == ISD::CopyFromReg) { in LowerArguments()
|
| H A D | SelectionDAGISel.cpp | 3209 case ISD::CopyFromReg: in SelectCodeCommon()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 259 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) { in SelectInlineAsmMemoryOperand()
309 SDValue CopyFromReg = in SelectInlineAsmMemoryOperand() local
312 OutOps.push_back(CopyFromReg); in SelectInlineAsmMemoryOperand()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 215 CopyFromReg, enumerator
|
| H A D | SelectionDAG.h | 814 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
824 return getNode(ISD::CopyFromReg, dl, VTs,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFragments.td | 688 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
691 // CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit
696 N->getOpcode() != ISD::CopyFromReg &&
|
| H A D | X86ISelLoweringCall.cpp | 2658 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
|
| H A D | X86ISelDAGToDAG.cpp | 390 if (OtherOp->getOpcode() == ISD::CopyFromReg && in shouldAvoidImmediateInstFormsForSize()
2639 RHS.getNode()->getOpcode() == ISD::CopyFromReg || in matchAddressRecursively()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 389 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
395 N->getOpcode() != ISD::CopyFromReg;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 323 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
2401 T1.getOpcode() != ISD::CopyFromReg && in LowerSELECT()
2402 T2.getOpcode() != ISD::CopyFromReg) { in LowerSELECT()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 869 setOperationAction(ISD::CopyFromReg, MVT::i128, Custom); in NVPTXTargetLowering()
6349 SDValue NewValue = DAG.getNode(ISD::CopyFromReg, DL, ResultsType, NewOps); in ReplaceCopyFromReg_128()
6369 case ISD::CopyFromReg: in ReplaceNodeResults()
|
| H A D | NVPTXISelDAGToDAG.cpp | 529 case ISD::CopyFromReg: { in Select()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 11979 case ISD::CopyFromReg: { in calculateByteProvider()
12341 for (auto VectorwiseOp : {ISD::STORE, ISD::CopyToReg, ISD::CopyFromReg}) in performOrCombine()
15946 assert(N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
15953 } while (N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
15961 case ISD::CopyFromReg: { in isSDNodeSourceOfDivergence()
|
| H A D | AMDGPUISelDAGToDAG.cpp | 1535 if (Val.getOpcode() != ISD::CopyFromReg) in IsCopyFromSGPR()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 809 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1463 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3661 if (Ptr.getOpcode() == ISD::CopyFromReg && in Select()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4668 return AddrOp.getOpcode() == ISD::CopyFromReg; in isOffsetMultipleOf()
|