Searched refs:Const1 (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | DIExpressionOptimizer.cpp | 45 foldOperationIfPossible(uint64_t Const1, uint64_t Const2, in foldOperationIfPossible() argument
51 auto Result = SaturatingAdd(Const1, Const2, &ResultOverflowed); in foldOperationIfPossible()
57 if (Const1 < Const2) in foldOperationIfPossible()
59 return Const1 - Const2; in foldOperationIfPossible()
62 if ((uint64_t)countl_zero(Const1) < Const2) in foldOperationIfPossible()
64 return Const1 << Const2; in foldOperationIfPossible()
67 if ((uint64_t)countr_zero(Const1) < Const2) in foldOperationIfPossible()
69 return Const1 >> Const2; in foldOperationIfPossible()
72 auto Result = SaturatingMultiply(Const1, Const2, &ResultOverflowed); in foldOperationIfPossible()
79 return Const1 / Const2; in foldOperationIfPossible()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 952 SDValue Const1; in performORCombine() local
955 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); in performORCombine()
956 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
2352 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); in lowerFCOPYSIGN32() local
2361 Const1); in lowerFCOPYSIGN32()
2365 Const1); in lowerFCOPYSIGN32()
2370 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); in lowerFCOPYSIGN32()
2371 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); in lowerFCOPYSIGN32()
2378 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); in lowerFCOPYSIGN32()
2379 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 3138 SDValue Const1 = DAG.getConstant(1, DL, MVT::i64); in lowerEXTRACT_VECTOR_ELT() local
3139 SDValue HalfIdx = DAG.getNode(ISD::SRL, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT()
3142 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT()
3143 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
3196 SDValue Const1 = DAG.getConstant(1, DL, MVT::i64); in lowerINSERT_VECTOR_ELT() local
3197 SDValue HalfIdx = DAG.getNode(ISD::SRL, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT()
3200 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT()
3201 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 8438 bool Const1 = isa<ConstantInt>(Op1) || isa<ConstantFP>(Op1) || in optimizeInst() local
8440 if (Const0 || Const1) { in optimizeInst()
8441 if (!Const0 || !Const1) { in optimizeInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2500 auto Const1 = B.buildConstant(S32, ExpBits); in extractF64Exponent() local
2505 .addUse(Const1.getReg(0)); in extractF64Exponent()
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