Home
last modified time | relevance | path

Searched refs:CondCode (Results 1 – 25 of 148) sorted by relevance

123456

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64GlobalISelUtils.cpp127 const CmpInst::Predicate P, AArch64CC::CondCode &CondCode, in changeFCMPPredToAArch64CC() argument
128 AArch64CC::CondCode &CondCode2) { in changeFCMPPredToAArch64CC()
134 CondCode = AArch64CC::EQ; in changeFCMPPredToAArch64CC()
137 CondCode = AArch64CC::GT; in changeFCMPPredToAArch64CC()
140 CondCode = AArch64CC::GE; in changeFCMPPredToAArch64CC()
143 CondCode = AArch64CC::MI; in changeFCMPPredToAArch64CC()
146 CondCode = AArch64CC::LS; in changeFCMPPredToAArch64CC()
149 CondCode = AArch64CC::MI; in changeFCMPPredToAArch64CC()
153 CondCode = AArch64CC::VC; in changeFCMPPredToAArch64CC()
156 CondCode = AArch64CC::VS; in changeFCMPPredToAArch64CC()
[all …]
H A DAArch64GlobalISelUtils.h69 AArch64CC::CondCode &CondCode,
70 AArch64CC::CondCode &CondCode2);
80 AArch64CC::CondCode &CondCode,
81 AArch64CC::CondCode &CondCode2,
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1685 enum CondCode { enum
1718 inline bool isSignedIntSetCC(CondCode Code) { in isSignedIntSetCC()
1724 inline bool isUnsignedIntSetCC(CondCode Code) { in isUnsignedIntSetCC()
1730 inline bool isIntEqualitySetCC(CondCode Code) { in isIntEqualitySetCC()
1736 inline bool isFPEqualitySetCC(CondCode Code) { in isFPEqualitySetCC()
1743 inline bool isTrueWhenEqual(CondCode Cond) { return ((int)Cond & 1) != 0; } in isTrueWhenEqual()
1748 inline unsigned getUnorderedFlavor(CondCode Cond) { in getUnorderedFlavor()
1754 LLVM_ABI CondCode getSetCCInverse(CondCode Operation, EVT Type);
1774 LLVM_ABI CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike);
1779 LLVM_ABI CondCode getSetCCSwappedOperands(CondCode Operation);
[all …]
H A DAnalysis.h109 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
113 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
117 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
121 ICmpInst::Predicate getICmpCondCode(ISD::CondCode Pred);
H A DSDPatternMatch.h659 SDValue FalseValue, ISD::CondCode CC) {
664 ISD::CondCode Cond =
710 static bool match(ISD::CondCode Cond) {
711 return Cond == ISD::CondCode::SETGT || Cond == ISD::CondCode::SETGE;
717 static bool match(ISD::CondCode Cond) {
718 return Cond == ISD::CondCode::SETUGT || Cond == ISD::CondCode::SETUGE;
724 static bool match(ISD::CondCode Cond) {
725 return Cond == ISD::CondCode::SETLT || Cond == ISD::CondCode::SETLE;
731 static bool match(ISD::CondCode Cond) {
732 return Cond == ISD::CondCode::SETULT || Cond == ISD::CondCode::SETULE;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp149 AArch64CC::CondCode &CondCode) const;
151 AArch64CC::CondCode &CondCode, DebugLoc DL) const;
183 AArch64CC::CondCode &CondCode) const { in endsWithCondControlFlow()
208 CondCode = AArch64CC::CondCode(analyzeBranchCondCode[0].getImm()); in endsWithCondControlFlow()
221 MachineBasicBlock &SplitEdgeBB, AArch64CC::CondCode &CondCode, in insertTrackingCode() argument
230 .addImm(CondCode); in insertTrackingCode()
242 AArch64CC::CondCode CondCode; in instrumentControlFlow() local
244 if (!endsWithCondControlFlow(MBB, TBB, FBB, CondCode)) { in instrumentControlFlow()
251 AArch64CC::CondCode InvCondCode = AArch64CC::getInvertedCondCode(CondCode); in instrumentControlFlow()
263 insertTrackingCode(*SplitEdgeTBB, CondCode, DL); in instrumentControlFlow()
H A DAArch64ConditionOptimizer.cpp102 using CmpInfo = std::tuple<int, unsigned, AArch64CC::CondCode>;
110 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
112 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
228 static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) { in getAdjustedCmp()
242 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) { in adjustCmp()
273 AArch64CC::CondCode Cmp; in modifyCmp()
302 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
306 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
316 AArch64CC::CondCode Cmp, MachineInstr *To, int ToImm) in adjustTo()
373 AArch64CC::CondCode HeadCmp; in runOnMachineFunction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVE.h43 enum CondCode { enum
86 inline static const char *VECondCodeToString(VECC::CondCode CC) { in VECondCodeToString()
115 inline static VECC::CondCode stringToVEICondCode(StringRef S) { in stringToVEICondCode()
116 return StringSwitch<VECC::CondCode>(S) in stringToVEICondCode()
129 inline static VECC::CondCode stringToVEFCondCode(StringRef S) { in stringToVEFCondCode()
130 return StringSwitch<VECC::CondCode>(S) in stringToVEFCondCode()
151 inline static bool isIntVECondCode(VECC::CondCode CC) { in isIntVECondCode()
155 inline static unsigned VECondCodeToVal(VECC::CondCode CC) { in VECondCodeToVal()
206 inline static VECC::CondCode VEValToCondCode(unsigned Val, bool IsInteger) { in VEValToCondCode()
H A DVEISelLowering.h69 inline static VECC::CondCode intCondCode2Icc(ISD::CondCode CC) { in intCondCode2Icc()
97 inline static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC) { in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiCondCode.h10 enum CondCode { enum
34 inline static StringRef lanaiCondCodeToString(LPCC::CondCode CC) { in lanaiCondCodeToString()
73 inline static CondCode suffixToLanaiCondCode(StringRef S) { in suffixToLanaiCondCode()
74 return StringSwitch<CondCode>(S) in suffixToLanaiCondCode()
H A DLanaiInstrInfo.cpp125 static LPCC::CondCode getOppositeCondition(LPCC::CondCode CC) { in getOppositeCondition()
354 SmallVector<std::pair<MachineOperand *, LPCC::CondCode>, 4> in optimizeCompareInstr()
374 LPCC::CondCode CC; in optimizeCompareInstr()
375 CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm(); in optimizeCompareInstr()
378 LPCC::CondCode NewCC = getOppositeCondition(CC); in optimizeCompareInstr()
522 unsigned CondCode = MI.getOperand(3).getImm(); in optimizeSelect() local
524 NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode))); in optimizeSelect()
526 NewMI.addImm(CondCode); in optimizeSelect()
623 LPCC::CondCode BranchCond = in analyzeBranch()
624 static_cast<LPCC::CondCode>(Instruction->getOperand(1).getImm()); in analyzeBranch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp33 enum CondCode { enum
129 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) in GetCondFromBranchOpc()
142 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) in GetCondBranchFromCond()
153 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) in GetOppositeBranchCondition()
208 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in analyzeBranch()
229 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); in analyzeBranch()
285 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
294 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
402 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in reverseBranchCondition()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp334 unsigned CondCode; in parseJccInstruction() local
336 CondCode = MSP430CC::COND_NE; in parseJccInstruction()
338 CondCode = MSP430CC::COND_E; in parseJccInstruction()
340 CondCode = MSP430CC::COND_LO; in parseJccInstruction()
342 CondCode = MSP430CC::COND_HS; in parseJccInstruction()
344 CondCode = MSP430CC::COND_N; in parseJccInstruction()
346 CondCode = MSP430CC::COND_GE; in parseJccInstruction()
348 CondCode = MSP430CC::COND_L; in parseJccInstruction()
350 CondCode = MSP430CC::COND_NONE; in parseJccInstruction()
354 if (CondCode == (unsigned)MSP430CC::COND_NONE) in parseJccInstruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h48 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
60 CondCode getCondFromMI(const MachineInstr &MI);
63 CondCode getCondFromBranch(const MachineInstr &MI);
66 CondCode getCondFromSETCC(const MachineInstr &MI);
69 CondCode getCondFromCMov(const MachineInstr &MI);
72 CondCode getCondFromCFCMov(const MachineInstr &MI);
75 CondCode getCondFromCCMP(const MachineInstr &MI);
78 int getCCMPCondFlagsFromCondCode(CondCode CC);
88 CondCode GetOppositeBranchCondition(CondCode CC);
91 unsigned getVPCMPImmForCond(ISD::CondCode CC);
H A DX86FlagsCopyLowering.cpp100 const DebugLoc &TestLoc, X86::CondCode Cond);
103 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
729 X86::CondCode Cond = X86::getCondFromSETCC(MI); in collectCondsInRegs()
747 const DebugLoc &TestLoc, X86::CondCode Cond) { in promoteCondToReg()
759 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs) { in getCondOrInverseInReg()
786 X86::CondCode Cond = X86::getCondFromSETCC(MI); in rewriteSetCC()
847 X86::CondCode Cond = X86::COND_B; // CF == 1 in rewriteArithmetic()
874 static X86::CondCode getImplicitCondFromMI(unsigned Opc) { in getImplicitCondFromMI()
896 static unsigned getOpcodeWithCC(unsigned Opc, X86::CondCode CC) { in getOpcodeWithCC()
924 X86::CondCode CC = X86::getCondFromMI(MI); in rewriteMI()
[all …]
H A DX86CmovConversion.cpp294 X86::CondCode FirstCC = X86::COND_INVALID, FirstOppCC = X86::COND_INVALID, in collectCmovCandidates()
306 X86::CondCode CC = X86::getCondFromCMov(I); in collectCmovCandidates()
669 X86::CondCode CC = X86::CondCode(X86::getCondFromCMov(MI)); in convertCmovInstsToBranches()
670 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC); in convertCmovInstsToBranches()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.h34 enum CondCode { enum
58 static inline M68k::CondCode GetOppositeBranchCondition(M68k::CondCode CC) { in GetOppositeBranchCondition()
97 static inline unsigned GetCondBranchFromCond(M68k::CondCode CC) { in GetCondBranchFromCond()
132 static inline M68k::CondCode GetCondFromBranchOpc(unsigned Opcode) { in GetCondFromBranchOpc()
H A DM68kISelLowering.cpp1655 static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, in getBitTestCondition()
1671 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition()
1677 static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL, in LowerAndToBTST()
1725 static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode) { in TranslateIntegerM68kCC()
1755 static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, in TranslateM68kCC()
1836 static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC, in LowerTruncateToBTST()
2134 SDValue M68kTargetLowering::LowerToBTST(SDValue Op, ISD::CondCode CC, in LowerToBTST()
2151 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
2175 M68k::CondCode CCode = (M68k::CondCode)Op0.getConstantOperandVal(0); in LowerSETCC()
2191 ISD::CondCode NewCC = ISD::GlobalISel::getSetCCInverse(CC, true); in LowerSETCC()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h37 enum CondCode { enum
47 CondCode getOppositeBranchCondition(CondCode);
48 unsigned getBrCond(CondCode CC, unsigned SelectOpc = 0);
313 static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc);
317 static bool evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0, int64_t C1);
H A DRISCVISelDAGToDAG.h97 bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val);
178 static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC) { in getRISCVCCForIntCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCInstPrinter.cpp54 static const char *ARCCondCodeToString(ARCCC::CondCode CC) { in ARCCondCodeToString()
172 O << ARCCondCodeToString((ARCCC::CondCode)Op.getImm()); in printPredicateOperand()
184 O << ARCCondCodeToString((ARCCC::CondCode)MI->getOperand(OpNum).getImm()); in printCCOperand()
H A DARCInfo.h24 enum CondCode { enum
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h254 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
281 inline static const char *getCondCodeName(CondCode Code) { in getCondCodeName()
303 inline static CondCode getInvertedCondCode(CondCode Code) { in getInvertedCondCode()
306 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); in getInvertedCondCode()
312 inline static CondCode getSwappedCondition(CondCode CC) { in getSwappedCondition()
343 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { in getNZCVToSatisfyCondCode()
367 inline static bool isValidCBCond(AArch64CC::CondCode Code) { in isValidCBCond()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp283 LPCC::CondCode CC = in printCCOperand()
284 static_cast<LPCC::CondCode>(MI->getOperand(OpNo).getImm()); in printCCOperand()
294 LPCC::CondCode CC = in printPredicateOperand()
295 static_cast<LPCC::CondCode>(MI->getOperand(OpNo).getImm()); in printPredicateOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.h32 enum CondCode { enum
72 const char *MipsFCCToString(Mips::CondCode CC);

123456