Searched refs:Cond0 (Results 1 – 3 of 3) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineSelect.cpp | 3396 static bool isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0, in isSafeToRemoveBitCeilSelect() argument 3450 if (MatchForward(Cond0)) { in isSafeToRemoveBitCeilSelect() 3452 } else if (match(Cond0, m_Add(m_Value(CommonAncestor), m_APInt(C)))) { in isSafeToRemoveBitCeilSelect() 3498 Value *Cond0, *Ctlz, *CtlzOp; in foldBitCeil() local 3499 if (!match(SI.getCondition(), m_ICmp(Pred, m_Value(Cond0), m_APInt(Cond1)))) in foldBitCeil() 3514 !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth, in foldBitCeil()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 11544 SDValue Cond0, Cond1; in foldVSelectToSignBitSplatMask() local 11546 if (!sd_match(N0, m_OneUse(m_SetCC(m_Value(Cond0), m_Value(Cond1), in foldVSelectToSignBitSplatMask() 11548 VT != Cond0.getValueType()) in foldVSelectToSignBitSplatMask() 11564 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask() 11572 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask() 11583 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask() 11638 SDValue Cond0 = N0->getOperand(0); in visitSELECT() local 11643 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, in visitSELECT() 11651 SDValue Cond0 = N0->getOperand(0); in visitSELECT() local 11656 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, N1, in visitSELECT() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 46158 SDValue Cond0 = Cond.getOperand(0); in combineSelect() local 46181 if (LHS == Cond0 && RHS == Cond1) { in combineSelect() 46185 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect() 46190 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect() 46208 Cond0 == InnerSetCC.getOperand(0) && in combineSelect() 46221 Cond = DAG.getSetCC(DL, CondVT, Cond0, Cond1, NewCC); in combineSelect() 47397 SDValue Cond0 = Cond.getOperand(0); in combineCMov() local 47398 if (Cond0.getOpcode() == ISD::TRUNCATE) in combineCMov() 47399 Cond0 = Cond0.getOperand(0); in combineCMov() 47401 if (Cond0 == TrueOp && Sub1C && Sub1C->getZExtValue() == 2) { in combineCMov()
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