Searched refs:CombineOpc (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 982 unsigned CombineOpc = 0) { in canCombine() argument
990 ((unsigned)MI->getOpcode() != CombineOpc && CombineOpc != 0)) in canCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 2484 unsigned CombineOpc) { in canCombine() argument
2491 if (!MI || MI->getParent() != &MBB || MI->getOpcode() != CombineOpc) in canCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 6593 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
6601 if (!MI || MI->getParent() != &MBB || (unsigned)MI->getOpcode() != CombineOpc) in canCombine()
6616 if (isCombineInstrSettingFlag(CombineOpc) && in canCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 3638 unsigned CombineOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); in SplitVecOp_VECREDUCE() local
3639 SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags()); in SplitVecOp_VECREDUCE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 24090 unsigned CombineOpc; in LowerVSETCC() local
24094 CombineOpc = X86ISD::FOR; in LowerVSETCC()
24099 CombineOpc = X86ISD::FAND; in LowerVSETCC()
24118 Cmp = DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1); in LowerVSETCC()
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