| /freebsd/contrib/llvm-project/llvm/lib/FuzzMutate/ |
| H A D | Operations.cpp | 149 Instruction::OtherOps CmpOp, in cmpOpDescriptor() argument
151 auto buildOp = [CmpOp, Pred](ArrayRef<Value *> Srcs, Instruction *Inst) { in cmpOpDescriptor()
152 return CmpInst::Create(CmpOp, Pred, Srcs[0], Srcs[1], "C", Inst); in cmpOpDescriptor()
155 switch (CmpOp) { in cmpOpDescriptor()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/FuzzMutate/ |
| H A D | Operations.h | 42 OpDescriptor cmpOpDescriptor(unsigned Weight, Instruction::OtherOps CmpOp,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 814 unsigned getCmpOperandFoldingProfit(Register CmpOp, MachineRegisterInfo &MRI) { in getCmpOperandFoldingProfit() argument
816 if (!MRI.hasOneNonDBGUse(CmpOp)) in getCmpOperandFoldingProfit()
833 MachineInstr *Def = getDefIgnoringCopies(CmpOp, MRI); in getCmpOperandFoldingProfit()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandPseudoInsts.cpp | 78 unsigned LdarOp, unsigned StlrOp, unsigned CmpOp,
237 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
270 BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
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| H A D | AArch64ISelLowering.cpp | 20103 SDValue CmpOp = Op->getOperand(2); in foldOverflowCheck() local
20104 if (!isCMP(CmpOp)) in foldOverflowCheck()
20108 if (!isOneConstant(CmpOp.getOperand(1))) in foldOverflowCheck()
20111 if (!isNullConstant(CmpOp.getOperand(0))) in foldOverflowCheck()
20115 SDValue CsetOp = CmpOp->getOperand(IsAdd ? 0 : 1); in foldOverflowCheck()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 345 multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val,
347 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$A, Val:$B),
349 def: Pat<(select (i1 (CmpOp Val:$A, Val:$B)), Val:$B, Val:$A),
354 SDPatternOperator Sel, SDPatternOperator CmpOp,
356 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)),
359 def: Pat<(Sel (CmpType (CmpOp CmpPred:$Vs, CmpPred:$Vt)),
1002 multiclass SelMinMax16_pats<PatFrag CmpOp, InstHexagon InstA,
1004 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)),
1007 def: Pat<(sext_inreg (select (i1 (CmpOp IsPosHalf:$Rs, IsPosHalf:$Rt)),
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| H A D | HexagonBitSimplify.cpp | 2617 MachineOperand &CmpOp = MI->getOperand(2); in simplifyRCmp0() local
2618 if (!CmpOp.isImm() || CmpOp.getImm() != 0) in simplifyRCmp0()
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| H A D | HexagonInstrInfo.cpp | 3526 const MachineOperand &CmpOp = GA.getOperand(2); in getCompoundOpcode() local
3527 if (!CmpOp.isImm()) in getCompoundOpcode()
3529 int V = CmpOp.getImm(); in getCompoundOpcode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstructionSelector.cpp | 1610 unsigned CmpOp = getFCmpOpcode(I.getOperand(1).getPredicate()); in selectFCmp() local
1611 return selectCmp(ResVReg, ResType, CmpOp, I); in selectFCmp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 3235 unsigned CmpOp = Subtarget.isPPC64() ? PPC::CMPD : PPC::CMPW; in expandPostRAPseudo() local
3236 BuildMI(MBB, MI, DL, get(CmpOp), PPC::CR7).addReg(Val).addReg(Val); in expandPostRAPseudo()
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| H A D | PPCISelLowering.cpp | 11231 SDValue CmpOp = Op.getOperand(2); in LowerATOMIC_CMP_SWAP() local
11234 if (DAG.MaskedValueIsZero(CmpOp, HighBits)) in LowerATOMIC_CMP_SWAP()
11240 DAG.getNode(ISD::AND, dl, MVT::i32, CmpOp, in LowerATOMIC_CMP_SWAP()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 2934 SDValue CmpOp = getValue(CB.CmpMHS); in visitSwitchCase() local
2935 EVT VT = CmpOp.getValueType(); in visitSwitchCase()
2938 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT), in visitSwitchCase()
2942 VT, CmpOp, DAG.getConstant(Low, dl, VT)); in visitSwitchCase()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3457 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) { in isAbsolute() argument
3461 (Pos == CmpOp || (Pos.getOpcode() == ISD::SIGN_EXTEND && in isAbsolute()
3462 Pos.getOperand(0) == CmpOp))); in isAbsolute()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 46998 SDValue CmpOp = EFLAGS.getOperand(0); in combineSetCCMOVMSK() local
46999 unsigned CmpBits = CmpOp.getValueSizeInBits(); in combineSetCCMOVMSK()
47003 if (CmpOp.getOpcode() == ISD::TRUNCATE) in combineSetCCMOVMSK()
47004 CmpOp = CmpOp.getOperand(0); in combineSetCCMOVMSK()
47007 if (CmpOp.getOpcode() != X86ISD::MOVMSK) in combineSetCCMOVMSK()
47010 SDValue Vec = CmpOp.getOperand(0); in combineSetCCMOVMSK()
47027 bool IsOneUse = CmpOp.getNode()->hasOneUse(); in combineSetCCMOVMSK()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.td | 2021 // "set.CmpOp{.ftz}.dtype.stype", where dtype is the type of the destination
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