| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ConditionOptimizer.cpp | 112 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
113 void modifyCmp(MachineInstr *CmpMI, const CmpInfo &Info);
114 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
244 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) { in adjustCmp() argument
245 unsigned Opc = CmpMI->getOpcode(); in adjustCmp()
257 const int OldImm = (int)CmpMI->getOperand(2).getImm(); in adjustCmp()
271 void AArch64ConditionOptimizer::modifyCmp(MachineInstr *CmpMI, in modifyCmp() argument
278 MachineBasicBlock *const MBB = CmpMI->getParent(); in modifyCmp()
281 BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc)) in modifyCmp()
282 .add(CmpMI->getOperand(0)) in modifyCmp()
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| H A D | AArch64ConditionalCompares.cpp | 155 MachineInstr *CmpMI; member in __anon79d718350111::SSACCmpConv
185 bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
381 const MachineInstr *CmpMI) { in canSpeculateInstrs() argument
425 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) { in canSpeculateInstrs()
556 CmpMI = findConvertibleCompare(CmpBB); in canConvert()
557 if (!CmpMI) in canConvert()
560 if (!canSpeculateInstrs(CmpBB, CmpMI)) { in canConvert()
652 switch (CmpMI->getOpcode()) { in convert()
688 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), in convert()
690 if (CmpMI->getOperand(FirstOp + 1).isReg()) in convert()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVEVPTBlockPass.cpp | 71 MachineBasicBlock::iterator CmpMI = MI; in findVCMPToFoldIntoVPST() local
72 while (CmpMI != MI->getParent()->begin()) { in findVCMPToFoldIntoVPST()
73 --CmpMI; in findVCMPToFoldIntoVPST()
74 if (CmpMI->modifiesRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
76 if (CmpMI->readsRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
80 if (CmpMI == MI) in findVCMPToFoldIntoVPST()
82 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode()); in findVCMPToFoldIntoVPST()
87 if (registerDefinedBetween(CmpMI->getOperand(1).getReg(), std::next(CmpMI), in findVCMPToFoldIntoVPST()
90 if (registerDefinedBetween(CmpMI->getOperand(2).getReg(), std::next(CmpMI), in findVCMPToFoldIntoVPST()
93 return &*CmpMI; in findVCMPToFoldIntoVPST()
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| H A D | ARMBaseInstrInfo.cpp | 2111 MachineInstr *CmpMI = findCMPToFoldIntoCBZ(LastMI, TRI); in isProfitableToIfCvt() local
2112 if (CmpMI) in isProfitableToIfCvt()
5604 MachineBasicBlock::iterator CmpMI = Br; in findCMPToFoldIntoCBZ() local
5605 while (CmpMI != Br->getParent()->begin()) { in findCMPToFoldIntoCBZ()
5606 --CmpMI; in findCMPToFoldIntoCBZ()
5607 if (CmpMI->modifiesRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
5609 if (CmpMI->readsRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
5615 if (CmpMI->getOpcode() != ARM::tCMPi8 && CmpMI->getOpcode() != ARM::t2CMPri) in findCMPToFoldIntoCBZ()
5617 Register Reg = CmpMI->getOperand(0).getReg(); in findCMPToFoldIntoCBZ()
5619 ARMCC::CondCodes Pred = getInstrPredicate(*CmpMI, PredReg); in findCMPToFoldIntoCBZ()
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| H A D | ARMConstantIslandPass.cpp | 1963 MachineInstr *CmpMI = findCMPToFoldIntoCBZ(Br.MI, TRI); in optimizeThumb2Branches() local
1964 if (!CmpMI || CmpMI->getOpcode() != ARM::tCMPi8) in optimizeThumb2Branches()
1967 ImmCmp.MI = CmpMI; in optimizeThumb2Branches()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 999 const auto &CmpMI = cast<GFCmp>(MI); in applyLowerVectorFCMP() local
1001 Register Dst = CmpMI.getReg(0); in applyLowerVectorFCMP()
1002 CmpInst::Predicate Pred = CmpMI.getCond(); in applyLowerVectorFCMP()
1003 Register LHS = CmpMI.getLHSReg(); in applyLowerVectorFCMP()
1004 Register RHS = CmpMI.getRHSReg(); in applyLowerVectorFCMP()
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| H A D | AArch64InstructionSelector.cpp | 4478 auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addUse(LHS); in emitFPCompare() local
4479 CmpMI.setMIFlags(MachineInstr::NoFPExcept); in emitFPCompare()
4481 CmpMI.addUse(RHS); in emitFPCompare()
4482 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI); in emitFPCompare()
4483 return &*CmpMI; in emitFPCompare()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 1204 auto &CmpMI = cast<GFCmp>(MI); in selectFPCompare() local
1205 CmpInst::Predicate Pred = CmpMI.getCond(); in selectFPCompare()
1207 Register DstReg = CmpMI.getReg(0); in selectFPCompare()
1208 Register LHS = CmpMI.getLHSReg(); in selectFPCompare()
1209 Register RHS = CmpMI.getRHSReg(); in selectFPCompare()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2762 bool PPCInstrInfo::optimizeCmpPostRA(MachineInstr &CmpMI) const { in optimizeCmpPostRA()
2763 MachineRegisterInfo *MRI = &CmpMI.getParent()->getParent()->getRegInfo(); in optimizeCmpPostRA()
2769 if (!analyzeCompare(CmpMI, SrcReg, SrcReg2, CmpMask, CmpValue)) in optimizeCmpPostRA()
2780 unsigned Opc = CmpMI.getOpcode(); in optimizeCmpPostRA()
2792 if (CmpMI.hasImplicitDef()) in optimizeCmpPostRA()
2796 MachineInstr *SrcMI = getDefMIPostRA(SrcReg, CmpMI, SrcRegHasOtherUse); in optimizeCmpPostRA()
2800 MachineOperand RegMO = CmpMI.getOperand(0); in optimizeCmpPostRA()
2808 if (!isRegElgibleForForwarding(RegMO, *SrcMI, CmpMI, false, IsCRRegKilled, in optimizeCmpPostRA()
2833 LLVM_DEBUG(CmpMI.dump()); in optimizeCmpPostRA()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIWholeQuadMode.cpp | 1584 auto CmpMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_CMP_EQ_U32)) in lowerInitExec() local
1603 LIS->InsertMachineInstrInMaps(*CmpMI); in lowerInitExec()
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