| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4796 EVT CastVT = in LowerVectorXRINT() local
4801 SDValue FOp = DAG.getNode(ISD::FRINT, DL, CastVT, Src); in LowerVectorXRINT()
4888 MVT CastVT = in LowerVectorINT_TO_FP() local
4892 In = DAG.getNode(Opc, DL, {CastVT, MVT::Other}, {Op.getOperand(0), In}); in LowerVectorINT_TO_FP()
4897 In = DAG.getNode(Opc, DL, CastVT, In); in LowerVectorINT_TO_FP()
4904 EVT CastVT = VT.changeVectorElementTypeToInteger(); in LowerVectorINT_TO_FP() local
4905 In = DAG.getNode(CastOpc, DL, CastVT, In); in LowerVectorINT_TO_FP()
6970 EVT CastVT = VecVT.changeVectorElementTypeToInteger(); in LowerVECTOR_COMPRESS() local
6975 Vec = DAG.getBitcast(CastVT, Vec); in LowerVECTOR_COMPRESS()
7004 CastVT = FixedVecVT.changeVectorElementTypeToInteger(); in LowerVECTOR_COMPRESS()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 3257 EVT CastVT = CastVal.getValueType(); in BitcastToInt_ATOMIC_SWAP() local
3260 = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, CastVT, in BitcastToInt_ATOMIC_SWAP()
3261 DAG.getVTList(CastVT, MVT::Other), in BitcastToInt_ATOMIC_SWAP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 13201 MVT CastVT = MVT::getVectorVT(VT.getVectorElementType(), NumSrcElts); in lowerShuffleAsBroadcast() local
13202 return DAG.getNode(Opcode, DL, VT, DAG.getBitcast(CastVT, V)); in lowerShuffleAsBroadcast()
18563 MVT CastVT = MVT::getVectorVT(MVT::i8, NumElts * 2); in LowerVSELECT() local
18564 Cond = DAG.getBitcast(CastVT, Cond); in LowerVSELECT()
18565 LHS = DAG.getBitcast(CastVT, LHS); in LowerVSELECT()
18566 RHS = DAG.getBitcast(CastVT, RHS); in LowerVSELECT()
18567 SDValue Select = DAG.getNode(ISD::VSELECT, dl, CastVT, Cond, LHS, RHS); in LowerVSELECT()
22860 EVT CastVT = VecVT; in combineVectorSizedSetCCEquality() local
22867 CastVT = VecVT; in combineVectorSizedSetCCEquality()
22871 CastVT = OpSize == 512 ? VecVT in combineVectorSizedSetCCEquality()
[all …]
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| H A D | X86InstrAVX512.td | 1709 X86VectorVTInfo CastVT> {
1713 (CastVT.VT _.RC:$src1))),
1715 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1721 (CastVT.VT _.RC:$src1))),
1723 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1728 (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))),
1730 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6348 EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT); in lowerIntrinsicLoad() local
6349 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other); in lowerIntrinsicLoad()
6350 SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT, in lowerIntrinsicLoad()
8318 static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT, in padEltsToUndef() argument
8333 return DAG.getBuildVector(CastVT, DL, Elts); in padEltsToUndef()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4859 MVT CastVT = ResVT.changeVectorElementType(VT.getVectorElementType()); in getDeinterleaveShiftAndTrunc() local
4860 Res = DAG.getBitcast(CastVT, Res); in getDeinterleaveShiftAndTrunc()
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