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Searched refs:CZERO_EQZ (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZicond.td18 def riscv_czero_eqz : SDNode<"RISCVISD::CZERO_EQZ", SDTIntBinOp>;
26 def CZERO_EQZ : ALU_rr<0b0000111, 0b101, "czero.eqz">,
38 (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
43 (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
49 (CZERO_EQZ GPR:$rs1, GPR:$rc)>;
H A DRISCVOptWInstrs.cpp329 case RISCV::CZERO_EQZ: in hasAllNBitUsers()
574 case RISCV::CZERO_EQZ: in isSignExtendedW()
H A DRISCVISelLowering.h408 CZERO_EQZ, // vt.maskc for XVentanaCondOps. enumerator
H A DRISCVISelLowering.cpp7708 // When Zicond or XVentanaCondOps is present, emit CZERO_EQZ and CZERO_NEZ in lowerSELECT()
7716 return DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV); in lowerSELECT()
7732 DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV)); in lowerSELECT()
7753 DAG.getNode(IsCZERO_NEZ ? RISCVISD::CZERO_NEZ : RISCVISD::CZERO_EQZ, in lowerSELECT()
7763 DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV), in lowerSELECT()
13735 if (N0.getOpcode() != RISCVISD::CZERO_EQZ || in combineOrOfCZERO()
13757 SDValue NewN0 = DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV.getOperand(0), in combineOrOfCZERO()
13778 // Look for Or of CZERO_EQZ/NEZ with same condition which is the select idiom. in performORCombine()
16881 case RISCVISD::CZERO_EQZ: in PerformDAGCombine()
16889 if (Opc == RISCVISD::CZERO_EQZ in PerformDAGCombine()
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