/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 3522 { ISD::CTTZ, MVT::v8i64, { 2, 8, 6, 7 } }, in getIntrinsicInstrCost() 3523 { ISD::CTTZ, MVT::v16i32, { 2, 8, 6, 7 } }, in getIntrinsicInstrCost() 3524 { ISD::CTTZ, MVT::v4i64, { 1, 8, 6, 6 } }, in getIntrinsicInstrCost() 3525 { ISD::CTTZ, MVT::v8i32, { 1, 8, 6, 6 } }, in getIntrinsicInstrCost() 3526 { ISD::CTTZ, MVT::v2i64, { 1, 8, 6, 6 } }, in getIntrinsicInstrCost() 3527 { ISD::CTTZ, MVT::v4i32, { 1, 8, 6, 6 } }, in getIntrinsicInstrCost() 3569 { ISD::CTTZ, MVT::v8i16, { 3, 9, 14, 14 } }, in getIntrinsicInstrCost() 3570 { ISD::CTTZ, MVT::v16i16, { 3, 9, 14, 14 } }, in getIntrinsicInstrCost() 3571 { ISD::CTTZ, MVT::v32i16, { 3, 10, 14, 16 } }, in getIntrinsicInstrCost() 3572 { ISD::CTTZ, MVT::v16i8, { 2, 6, 11, 11 } }, in getIntrinsicInstrCost() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCExpandPseudos.cpp | 150 case ARC::CTTZ: in runOnMachineFunction()
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H A D | ARCISelLowering.cpp | 172 setOperationAction(ISD::CTTZ, MVT::i32, Legal); in ARCTargetLowering()
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H A D | ARCInstrInfo.td | 143 def CTTZ : PseudoInstARC<(outs GPR32:$A),
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 743 CTTZ, enumerator
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H A D | BasicTTIImpl.h | 2321 ISD = ISD::CTTZ; in getTypeBasedIntrinsicInstrCost()
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 104 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering() 105 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 655 setOperationAction(ISD::CTTZ, MVT::i32, Legal); in AArch64TargetLowering() 656 setOperationAction(ISD::CTTZ, MVT::i64, Legal); in AArch64TargetLowering() 657 setOperationAction(ISD::CTTZ, MVT::i128, Expand); in AArch64TargetLowering() 1337 setOperationAction(ISD::CTTZ, VT, Expand); in AArch64TargetLowering() 1435 setOperationAction(ISD::CTTZ, VT, Custom); in AArch64TargetLowering() 1713 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in AArch64TargetLowering() 1735 setOperationAction(ISD::CTTZ, VT, Custom); in AArch64TargetLowering() 2047 setOperationAction(ISD::CTTZ, VT, Default); in addTypeForFixedLengthSVE() 7030 case ISD::CTTZ: in LowerOperation() 23695 SDValue Zero, CTTZ; in foldCSELofCTTZ() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 254 setOperationAction(ISD::CTTZ, MVT::v16i8, Expand); in WebAssemblyTargetLowering() 257 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}) in WebAssemblyTargetLowering() 1506 case ISD::CTTZ: in LowerOperation()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 486 case ISD::CTTZ: return "cttz"; in getOperationName()
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H A D | LegalizeVectorOps.cpp | 379 case ISD::CTTZ: in LegalizeOp() 978 case ISD::CTTZ: in Expand()
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H A D | LegalizeIntegerTypes.cpp | 78 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; in PromoteIntegerResult() 749 !TLI.isOperationLegalOrCustomOrPromote(ISD::CTTZ, NVT) && in PromoteIntRes_CTTZ() 760 if (NewOpc == ISD::CTTZ || NewOpc == ISD::VP_CTTZ) { in PromoteIntRes_CTTZ() 766 if (NewOpc == ISD::CTTZ) { in PromoteIntRes_CTTZ() 2795 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; in ExpandIntegerResult()
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H A D | LegalizeDAG.cpp | 3086 case ISD::CTTZ: in ExpandNode() 5114 case ISD::CTTZ: in PromoteNode() 5119 if (Node->getOpcode() == ISD::CTTZ || in PromoteNode() 5126 if (NewOpc == ISD::CTTZ) { in PromoteNode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 116 setOperationAction(ISD::CTTZ, VT, Expand); in BPFTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 220 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering() 294 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering() 1869 // Lower vector CTTZ into a computation using CTLZ (Hacker's Delight): in LowerHvxCttz() 3164 case ISD::CTTZ: in LowerHvxOperation() 3214 case ISD::CTTZ: return LowerHvxCttz(Op, DAG); in LowerHvxOperation()
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H A D | HexagonISelLowering.cpp | 1580 setOperationAction(ISD::CTTZ, MVT::i8, Promote); in HexagonTargetLowering() 1581 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in HexagonTargetLowering() 1651 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::BSWAP, ISD::BITREVERSE, in HexagonTargetLowering()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | VPIntrinsics.def | 279 VP_PROPERTY_FUNCTIONAL_SDOPC(CTTZ)
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 530 ISD::BITREVERSE, ISD::CTLZ, ISD::CTPOP, ISD::CTTZ, in NVPTXTargetLowering() 718 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in NVPTXTargetLowering() 719 setOperationAction(ISD::CTTZ, MVT::v2i16, Expand); in NVPTXTargetLowering() 720 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in NVPTXTargetLowering() 721 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in NVPTXTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 472 setOperationAction({ISD::BSWAP, ISD::CTTZ, ISD::CTLZ}, VT, Expand); in AMDGPUTargetLowering() 497 {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, in AMDGPUTargetLowering() 519 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering() 1406 case ISD::CTTZ: in LowerOperation() 3113 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF; in isCttzOpc()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
H A D | CSKYISelLowering.cpp | 105 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in CSKYTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 128 setOperationAction(ISD::CTTZ, MVT::i32, Legal); in LanaiTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 386 setOperationAction(ISD::CTTZ, MVT::i32, Legal); in RISCVTargetLowering() 388 setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom); in RISCVTargetLowering() 391 setOperationAction({ISD::CTTZ, ISD::CTPOP}, XLenVT, Expand); in RISCVTargetLowering() 393 setOperationAction({ISD::CTTZ, ISD::CTPOP}, MVT::i32, Expand); in RISCVTargetLowering() 915 setOperationAction({ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}, VT, Expand); in RISCVTargetLowering() 1272 ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTPOP}, in RISCVTargetLowering() 5971 OP_CASE(CTTZ) in getRISCVVLOp() 6028 VP_CASE(CTTZ) // VP_CTTZ in getRISCVVLOp() 7067 case ISD::CTTZ: in LowerOperation() 7071 assert(Op.getOpcode() != ISD::CTTZ); in LowerOperation() [all...] |
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1753 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering() 1815 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 279 setOperationAction(ISD::CTTZ, VT, Custom); in addMVEVectorTypes() 978 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom); in ARMTargetLowering() 979 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom); in ARMTargetLowering() 980 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom); in ARMTargetLowering() 981 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in ARMTargetLowering() 983 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom); in ARMTargetLowering() 984 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom); in ARMTargetLowering() 985 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom); in ARMTargetLowering() 986 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom); in ARMTargetLowering() 1206 setOperationAction(ISD::CTTZ, MVT::i32, Custom); in ARMTargetLowering() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchISelLowering.cpp | 133 setOperationAction(ISD::CTTZ, MVT::i32, Custom); in LoongArchTargetLowering() 2635 case ISD::CTTZ: in getLoongArchWOpcode() 2930 case ISD::CTTZ: { in ReplaceNodeResults()
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