1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 /*
31 * USBPHY driver for Freescale i.MX6 family of SoCs.
32 */
33
34 #include "opt_bus.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/bus.h>
41 #include <sys/rman.h>
42
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #include <machine/bus.h>
47
48 #include <arm/freescale/imx/imx_ccmvar.h>
49 #include <arm/freescale/imx/imx6_anatopreg.h>
50 #include <arm/freescale/imx/imx6_anatopvar.h>
51
52 /*
53 * Hardware register defines.
54 */
55 #define PWD_REG 0x0000
56 #define CTRL_STATUS_REG 0x0030
57 #define CTRL_SET_REG 0x0034
58 #define CTRL_CLR_REG 0x0038
59 #define CTRL_TOGGLE_REG 0x003c
60 #define CTRL_SFTRST (1U << 31)
61 #define CTRL_CLKGATE (1 << 30)
62 #define CTRL_ENUTMILEVEL3 (1 << 15)
63 #define CTRL_ENUTMILEVEL2 (1 << 14)
64
65 struct usbphy_softc {
66 device_t dev;
67 struct resource *mem_res;
68 u_int phy_num;
69 };
70
71 static struct ofw_compat_data compat_data[] = {
72 {"fsl,imx6q-usbphy", true},
73 {"fsl,imx6ul-usbphy", true},
74 {NULL, false}
75 };
76
77 static int
usbphy_detach(device_t dev)78 usbphy_detach(device_t dev)
79 {
80 struct usbphy_softc *sc;
81
82 sc = device_get_softc(dev);
83
84 if (sc->mem_res != NULL)
85 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
86
87 return (0);
88 }
89
90 static int
usbphy_attach(device_t dev)91 usbphy_attach(device_t dev)
92 {
93 struct usbphy_softc *sc;
94 int err, regoff, rid;
95
96 sc = device_get_softc(dev);
97 err = 0;
98
99 /* Allocate bus_space resources. */
100 rid = 0;
101 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
102 RF_ACTIVE);
103 if (sc->mem_res == NULL) {
104 device_printf(dev, "Cannot allocate memory resources\n");
105 err = ENXIO;
106 goto out;
107 }
108
109 /*
110 * XXX Totally lame way to get the unit number (but not quite as lame as
111 * adding an ad-hoc property to the fdt data). This works as long as
112 * this driver is used for imx6 only.
113 */
114 const uint32_t PWD_PHY1_REG_PHYSADDR = 0x020c9000;
115 if (BUS_SPACE_PHYSADDR(sc->mem_res, 0) == PWD_PHY1_REG_PHYSADDR) {
116 sc->phy_num = 0;
117 regoff = 0;
118 } else {
119 sc->phy_num = 1;
120 regoff = 0x60;
121 }
122
123 /*
124 * Based on a note in the u-boot source code, disable charger detection
125 * to avoid degrading the differential signaling on the DP line. Note
126 * that this disables (by design) both charger detection and contact
127 * detection, because of the screwball mix of active-high and active-low
128 * bits in this register.
129 */
130 imx6_anatop_write_4(IMX6_ANALOG_USB1_CHRG_DETECT + regoff,
131 IMX6_ANALOG_USB_CHRG_DETECT_N_ENABLE |
132 IMX6_ANALOG_USB_CHRG_DETECT_N_CHK_CHRG);
133
134 imx6_anatop_write_4(IMX6_ANALOG_USB1_CHRG_DETECT + regoff,
135 IMX6_ANALOG_USB_CHRG_DETECT_N_ENABLE |
136 IMX6_ANALOG_USB_CHRG_DETECT_N_CHK_CHRG);
137
138 /* XXX Configure the overcurrent detection here. */
139
140 /*
141 * Turn on the phy clocks.
142 */
143 imx_ccm_usbphy_enable(dev);
144
145 /*
146 * Set the software reset bit, then clear both it and the clock gate bit
147 * to bring the device out of reset with the clock running.
148 */
149 bus_write_4(sc->mem_res, CTRL_SET_REG, CTRL_SFTRST);
150 bus_write_4(sc->mem_res, CTRL_CLR_REG, CTRL_SFTRST | CTRL_CLKGATE);
151
152 /* Set UTMI+ level 2+3 bits to enable low and full speed devices. */
153 bus_write_4(sc->mem_res, CTRL_SET_REG,
154 CTRL_ENUTMILEVEL2 | CTRL_ENUTMILEVEL3);
155
156 /* Power up: clear all bits in the powerdown register. */
157 bus_write_4(sc->mem_res, PWD_REG, 0);
158
159 err = 0;
160
161 out:
162
163 if (err != 0)
164 usbphy_detach(dev);
165
166 return (err);
167 }
168
169 static int
usbphy_probe(device_t dev)170 usbphy_probe(device_t dev)
171 {
172
173 if (!ofw_bus_status_okay(dev))
174 return (ENXIO);
175
176 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
177 return (ENXIO);
178
179 device_set_desc(dev, "Freescale i.MX6 USB PHY");
180
181 return (BUS_PROBE_DEFAULT);
182 }
183
184 static device_method_t usbphy_methods[] = {
185 /* Device interface */
186 DEVMETHOD(device_probe, usbphy_probe),
187 DEVMETHOD(device_attach, usbphy_attach),
188 DEVMETHOD(device_detach, usbphy_detach),
189
190 DEVMETHOD_END
191 };
192
193 static driver_t usbphy_driver = {
194 "usbphy",
195 usbphy_methods,
196 sizeof(struct usbphy_softc)
197 };
198
199 /*
200 * This driver needs to start before the ehci driver, but later than the usual
201 * "special" drivers like clocks and cpu. Ehci starts at DEFAULT so SUPPORTDEV
202 * is where this driver fits most.
203 */
204 EARLY_DRIVER_MODULE(usbphy, simplebus, usbphy_driver, 0, 0,
205 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
206