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Searched refs:CSR_READ_2 (Results 1 – 25 of 38) sorted by relevance

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/freebsd/sys/dev/vte/
H A Dif_vte.c179 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) in vte_miibus_readreg()
188 return (CSR_READ_2(sc, VTE_MMRD)); in vte_miibus_readreg()
204 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) in vte_miibus_writereg()
360 mid = CSR_READ_2(sc, VTE_MID0L); in vte_get_macaddr()
363 mid = CSR_READ_2(sc, VTE_MID0M); in vte_get_macaddr()
366 mid = CSR_READ_2(sc, VTE_MID0H); in vte_get_macaddr()
409 CSR_READ_2(sc, VTE_MACID)); in vte_attach()
410 macid = CSR_READ_2(sc, VTE_MACID_REV); in vte_attach()
1226 mcr = CSR_READ_2(sc, VTE_MCR0); in vte_mac_config()
1251 CSR_READ_2(sc, VTE_CNT_RX_DONE); in vte_stats_clear()
[all …]
H A Dif_vtevar.h151 #define CSR_READ_2(_sc, reg) \ macro
/freebsd/sys/dev/ste/
H A Dif_ste.c189 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
192 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
281 cfg = CSR_READ_2(sc, STE_MACCTL0); in ste_miibus_statchg()
366 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) in ste_eeprom_wait()
397 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA)); in ste_read_eeprom()
489 status = CSR_READ_2(sc, STE_ISR_ACK); in ste_poll_locked()
521 status = CSR_READ_2(sc, STE_ISR_ACK); in ste_intr()
687 txstat = CSR_READ_2(sc, STE_TX_STATUS); in ste_txeoc()
811 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); in ste_stats_clear()
812 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); in ste_stats_clear()
[all …]
H A Dif_stereg.h490 #define CSR_READ_2(sc, reg) \ macro
/freebsd/sys/dev/vge/
H A Dif_vgevar.h226 #define CSR_READ_2(sc, reg) \ macro
234 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
241 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd/sys/dev/stge/
H A Dif_stge.c381 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) in stge_eeprom_wait()
403 *data = CSR_READ_2(sc, STGE_EepromData); in stge_read_eeprom()
541 v = CSR_READ_2(sc, STGE_StationAddress0); in stge_attach()
544 v = CSR_READ_2(sc, STGE_StationAddress1); in stge_attach()
547 v = CSR_READ_2(sc, STGE_StationAddress2); in stge_attach()
1457 status = CSR_READ_2(sc, STGE_IntStatus); in stge_intr()
1463 status = CSR_READ_2(sc, STGE_IntStatusAck); in stge_intr()
1788 status = CSR_READ_2(sc, STGE_IntStatus); in stge_poll()
1867 if_inc_counter(ifp, IFCOUNTER_IERRORS, CSR_READ_2(sc, STGE_FramesLostRxErrors)); in stge_stats_update()
1879 CSR_READ_2(sc, STGE_FramesAbortXSColls) + in stge_stats_update()
[all …]
H A Dif_stgereg.h98 #define CSR_READ_2(_sc, reg) \ macro
/freebsd/sys/dev/bwi/
H A Dbwirf.c221 return CSR_READ_2(sc, BWI_RF_DATA_LO); in bwi_rf_read()
252 val = CSR_READ_2(sc, BWI_RF_DATA_HI); in bwi_rf_attach()
256 val |= CSR_READ_2(sc, BWI_RF_DATA_LO); in bwi_rf_attach()
783 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL); in bwi_rf_init_bcm2050()
820 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN); in bwi_rf_init_bcm2050()
821 rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX); in bwi_rf_init_bcm2050()
1281 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); in bwi_rf_lo_update_11g()
1283 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX); in bwi_rf_lo_update_11g()
1662 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); in bwi_rf_calc_nrssi_slope_11b()
1663 CSR_READ_2(sc, BWI_BBP_ATTEN); in bwi_rf_calc_nrssi_slope_11b()
[all …]
H A Dif_bwivar.h78 #define CSR_READ_2(sc, reg) \ macro
89 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
94 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
99 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
H A Dbwimac.c174 return CSR_READ_2(sc, data_reg); in bwi_memobj_read_2()
188 ret = CSR_READ_2(sc, BWI_MOBJ_DATA_UNALIGN); in bwi_memobj_read_4()
193 ret |= CSR_READ_2(sc, BWI_MOBJ_DATA); in bwi_memobj_read_4()
735 if (CSR_READ_2(sc, 0x50e) & 0x80) in bwi_mac_dummy_xmit()
740 if (CSR_READ_2(sc, 0x50e) & 0x400) in bwi_mac_dummy_xmit()
745 if ((CSR_READ_2(sc, 0x690) & 0x100) == 0) in bwi_mac_dummy_xmit()
1947 CSR_READ_2(sc, BWI_PHYINFO); /* dummy read */ in bwi_mac_unlock()
H A Dbwiphy.c149 return CSR_READ_2(sc, BWI_PHY_DATA); in bwi_phy_read()
162 val = CSR_READ_2(sc, BWI_PHYINFO); in bwi_phy_attach()
/freebsd/sys/dev/vr/
H A Dif_vrreg.h753 #define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg) macro
759 #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
760 #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
H A Dif_vr.c259 return (CSR_READ_2(sc, VR_MIIDATA)); in vr_miibus_readreg()
1609 status = CSR_READ_2(sc, VR_ISR); in vr_poll_locked()
1670 status = CSR_READ_2(sc, VR_ISR); in vr_intr()
1696 status = CSR_READ_2(sc, VR_ISR); in vr_int_task()
1734 status = CSR_READ_2(sc, VR_ISR); in vr_int_task()
/freebsd/sys/dev/rl/
H A Dif_rl.c427 return (CSR_READ_2(sc, rl8139_reg)); in rl_miibus_readreg()
1124 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; in rl_rxeof()
1127 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; in rl_rxeof()
1316 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) { in rl_twister_update()
1332 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; in rl_twister_update()
1361 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; in rl_twister_update()
1459 status = CSR_READ_2(sc, RL_ISR); in rl_poll_locked()
1496 status = CSR_READ_2(sc, RL_ISR); in rl_intr()
1517 status = CSR_READ_2(sc, RL_ISR); in rl_intr()
H A Dif_rlreg.h956 #define CSR_READ_2(sc, reg) \ macro
971 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
974 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
/freebsd/sys/dev/xl/
H A Dif_xl.c358 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) in xl_wait()
388 val = CSR_READ_2(sc, XL_W4_PHY_MGMT); in xl_mii_bitbang_read()
530 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) in xl_eeprom_wait()
579 word = CSR_READ_2(sc, XL_W0_EE_DATA); in xl_read_eeprom()
746 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); in xl_setmode()
856 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) in xl_reset()
880 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | in xl_reset()
1359 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); in xl_attach()
2152 status = CSR_READ_2(sc, XL_STATUS); in xl_intr()
2239 status = CSR_READ_2(sc, XL_STATUS); in xl_poll_locked()
[all …]
H A Dif_xlreg.h661 #define CSR_READ_2(sc, reg) \ macro
/freebsd/sys/dev/fxp/
H A Dif_fxpvar.h245 #define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg) macro
/freebsd/sys/dev/ale/
H A Dif_alevar.h235 #define CSR_READ_2(_sc, reg) \ macro
/freebsd/sys/dev/alc/
H A Dif_alcvar.h266 #define CSR_READ_2(_sc, reg) \ macro
/freebsd/sys/dev/age/
H A Dif_agevar.h241 #define CSR_READ_2(_sc, reg) \ macro
/freebsd/sys/dev/ipw/
H A Dif_ipwreg.h329 #define CSR_READ_2(sc, reg) \ macro
/freebsd/sys/dev/my/
H A Dif_myreg.h397 #define CSR_READ_2(sc, reg) \ macro
/freebsd/sys/dev/lge/
H A Dif_lgereg.h535 #define CSR_READ_2(sc, reg) \ macro
/freebsd/sys/dev/re/
H A Dif_re.c562 rval = CSR_READ_2(sc, re8139_reg); in re_miibus_readreg()
850 status = CSR_READ_2(sc, RL_ISR); in re_diag()
2535 status = CSR_READ_2(sc, RL_ISR); in re_poll_locked()
2565 status = CSR_READ_2(sc, RL_ISR); in re_intr()
2588 status = CSR_READ_2(sc, RL_ISR); in re_int_task()
2637 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { in re_int_task()
2670 status = CSR_READ_2(sc, RL_ISR); in re_intr_msi()

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