Searched refs:CLK_UART0_DIV (Results 1 – 4 of 4) sorted by relevance
67 #define CLK_UART0_DIV 77 macro
22 #define CLK_UART0_DIV 9 macro
173 GATE(CLK_UART0_DIV, "sclk_uart0_div", "sclk_uart0_div_div", 1, 3),
260 <&clk_core CLK_UART0_DIV>;