Searched refs:CLK_TOP_UNIVPLL_D5_D4 (Results 1 – 8 of 8) sorted by relevance
106 #define CLK_TOP_UNIVPLL_D5_D4 70 macro
111 #define CLK_TOP_UNIVPLL_D5_D4 92 macro
81 #define CLK_TOP_UNIVPLL_D5_D4 71 macro
105 #define CLK_TOP_UNIVPLL_D5_D4 93 macro
129 #define CLK_TOP_UNIVPLL_D5_D4 118 macro
162 #define CLK_TOP_UNIVPLL_D5_D4 150 macro
1361 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,1362 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;1439 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,1440 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;1463 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,1464 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;1487 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,1488 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
957 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,958 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;