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Searched refs:CLK_PCIEPHY0_DIV (Results 1 – 2 of 2) sorted by relevance

/freebsd/sys/dev/clk/rockchip/
H A Drk3568_pmucru.c193 GATE(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "clk_pciephy0_div_div", 2, 7),
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Drk3568-cru.h42 #define CLK_PCIEPHY0_DIV 29 macro