1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019-2020 Thomas Skibo <thomasskibo@yahoo.com>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 /* Cadence / Zynq i2c driver.
29 *
30 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
31 * (v1.12.2) July 1, 2018. Xilinx doc UG585. I2C Controller is documented
32 * in Chapter 20.
33 */
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/conf.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/sysctl.h>
41 #include <sys/lock.h>
42 #include <sys/mutex.h>
43 #include <sys/resource.h>
44 #include <sys/rman.h>
45 #include <sys/uio.h>
46
47 #include <machine/bus.h>
48 #include <machine/resource.h>
49 #include <machine/stdarg.h>
50
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54
55 #include <dev/clk/clk.h>
56
57 #include <dev/iicbus/iiconf.h>
58 #include <dev/iicbus/iicbus.h>
59
60 #include "iicbus_if.h"
61
62 #ifdef I2CDEBUG
63 #define DPRINTF(...) do { printf(__VA_ARGS__); } while (0)
64 #else
65 #define DPRINTF(...) do { } while (0)
66 #endif
67
68 #if 0
69 #define HWTYPE_CDNS_R1P10 1
70 #endif
71 #define HWTYPE_CDNS_R1P14 2
72
73 static struct ofw_compat_data compat_data[] = {
74 #if 0
75 {"cdns,i2c-r1p10", HWTYPE_CDNS_R1P10},
76 #endif
77 {"cdns,i2c-r1p14", HWTYPE_CDNS_R1P14},
78 {NULL, 0}
79 };
80
81 struct cdnc_i2c_softc {
82 device_t dev;
83 device_t iicbus;
84 struct mtx sc_mtx;
85 struct resource *mem_res;
86 struct resource *irq_res;
87 void *intrhandle;
88
89 uint16_t cfg_reg_shadow;
90 uint16_t istat;
91 clk_t ref_clk;
92 uint32_t ref_clock_freq;
93 uint32_t i2c_clock_freq;
94
95 int hwtype;
96 int hold;
97
98 /* sysctls */
99 unsigned int i2c_clk_real_freq;
100 unsigned int interrupts;
101 unsigned int timeout_ints;
102 };
103
104 #define I2C_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
105 #define I2C_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
106 #define I2C_SC_LOCK_INIT(sc) \
107 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF)
108 #define I2C_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx)
109 #define I2C_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
110
111 #define RD2(sc, off) (bus_read_2((sc)->mem_res, (off)))
112 #define WR2(sc, off, val) (bus_write_2((sc)->mem_res, (off), (val)))
113 #define RD1(sc, off) (bus_read_1((sc)->mem_res, (off)))
114 #define WR1(sc, off, val) (bus_write_1((sc)->mem_res, (off), (val)))
115
116 /* Cadence I2C controller device registers. */
117 #define CDNC_I2C_CR 0x0000 /* Config register. */
118 #define CDNC_I2C_CR_DIV_A_MASK (3 << 14)
119 #define CDNC_I2C_CR_DIV_A_SHIFT 14
120 #define CDNC_I2C_CR_DIV_A(a) ((a) << 14)
121 #define CDNC_I2C_CR_DIV_A_MAX 3
122 #define CDNC_I2C_CR_DIV_B_MASK (0x3f << 8)
123 #define CDNC_I2C_CR_DIV_B_SHIFT 8
124 #define CDNC_I2C_CR_DIV_B(b) ((b) << 8)
125 #define CDNC_I2C_CR_DIV_B_MAX 63
126 #define CDNC_I2C_CR_CLR_FIFO (1 << 6)
127 #define CDNC_I2C_CR_SLVMON_MODE (1 << 5)
128 #define CDNC_I2C_CR_HOLD (1 << 4)
129 #define CDNC_I2C_CR_ACKEN (1 << 3)
130 #define CDNC_I2C_CR_NEA (1 << 2)
131 #define CDNC_I2C_CR_MAST (1 << 1)
132 #define CDNC_I2C_CR_RNW (1 << 0)
133
134 #define CDNC_I2C_SR 0x0004 /* Status register. */
135 #define CDNC_I2C_SR_BUS_ACTIVE (1 << 8)
136 #define CDNC_I2C_SR_RX_OVF (1 << 7)
137 #define CDNC_I2C_SR_TX_VALID (1 << 6)
138 #define CDNC_I2C_SR_RX_VALID (1 << 5)
139 #define CDNC_I2C_SR_RXRW (1 << 3)
140
141 #define CDNC_I2C_ADDR 0x0008 /* i2c address register. */
142 #define CDNC_I2C_DATA 0x000C /* i2c data register. */
143
144 #define CDNC_I2C_ISR 0x0010 /* Int status register. */
145 #define CDNC_I2C_ISR_ARB_LOST (1 << 9)
146 #define CDNC_I2C_ISR_RX_UNDF (1 << 7)
147 #define CDNC_I2C_ISR_TX_OVF (1 << 6)
148 #define CDNC_I2C_ISR_RX_OVF (1 << 5)
149 #define CDNC_I2C_ISR_SLV_RDY (1 << 4)
150 #define CDNC_I2C_ISR_XFER_TMOUT (1 << 3)
151 #define CDNC_I2C_ISR_XFER_NACK (1 << 2)
152 #define CDNC_I2C_ISR_XFER_DATA (1 << 1)
153 #define CDNC_I2C_ISR_XFER_DONE (1 << 0)
154 #define CDNC_I2C_ISR_ALL 0x2ff
155 #define CDNC_I2C_TRANS_SIZE 0x0014 /* Transfer size. */
156 #define CDNC_I2C_PAUSE 0x0018 /* Slv Monitor Pause reg. */
157 #define CDNC_I2C_TIME_OUT 0x001C /* Time-out register. */
158 #define CDNC_I2C_TIME_OUT_MIN 31
159 #define CDNC_I2C_TIME_OUT_MAX 255
160 #define CDNC_I2C_IMR 0x0020 /* Int mask register. */
161 #define CDNC_I2C_IER 0x0024 /* Int enable register. */
162 #define CDNC_I2C_IDR 0x0028 /* Int disable register. */
163
164 #define CDNC_I2C_FIFO_SIZE 16
165 #define CDNC_I2C_DEFAULT_I2C_CLOCK 400000 /* 400Khz default */
166
167 #define CDNC_I2C_ISR_ERRS (CDNC_I2C_ISR_ARB_LOST | CDNC_I2C_ISR_RX_UNDF | \
168 CDNC_I2C_ISR_TX_OVF | CDNC_I2C_ISR_RX_OVF | CDNC_I2C_ISR_XFER_TMOUT | \
169 CDNC_I2C_ISR_XFER_NACK)
170
171 /* Configure clock dividers. */
172 static int
cdnc_i2c_set_freq(struct cdnc_i2c_softc * sc)173 cdnc_i2c_set_freq(struct cdnc_i2c_softc *sc)
174 {
175 uint32_t div_a, div_b, err, clk_out;
176 uint32_t best_div_a, best_div_b, best_err;
177
178 best_div_a = 0;
179 best_div_b = 0;
180 best_err = ~0U;
181
182 /*
183 * The i2c controller has a two-stage clock divider to create
184 * the "clock enable" signal used to sample the incoming SCL and
185 * SDA signals. The Clock Enable signal is divided by 22 to create
186 * the outgoing SCL signal.
187 *
188 * Try all div_a values and pick best match.
189 */
190 for (div_a = 0; div_a <= CDNC_I2C_CR_DIV_A_MAX; div_a++) {
191 div_b = sc->ref_clock_freq / (22 * sc->i2c_clock_freq *
192 (div_a + 1));
193 if (div_b > CDNC_I2C_CR_DIV_B_MAX)
194 continue;
195 clk_out = sc->ref_clock_freq / (22 * (div_a + 1) *
196 (div_b + 1));
197 err = clk_out > sc->i2c_clock_freq ?
198 clk_out - sc->i2c_clock_freq :
199 sc->i2c_clock_freq - clk_out;
200 if (err < best_err) {
201 best_err = err;
202 best_div_a = div_a;
203 best_div_b = div_b;
204 }
205 }
206
207 if (best_err == ~0U) {
208 device_printf(sc->dev, "cannot configure clock divider.\n");
209 return (EINVAL); /* out of range */
210 }
211
212 clk_out = sc->ref_clock_freq / (22 * (best_div_a + 1) *
213 (best_div_b + 1));
214
215 DPRINTF("%s: ref_clock_freq=%d i2c_clock_freq=%d\n", __func__,
216 sc->ref_clock_freq, sc->i2c_clock_freq);
217 DPRINTF("%s: div_a=%d div_b=%d real-freq=%d\n", __func__, best_div_a,
218 best_div_b, clk_out);
219
220 sc->cfg_reg_shadow &= ~(CDNC_I2C_CR_DIV_A_MASK |
221 CDNC_I2C_CR_DIV_B_MASK);
222 sc->cfg_reg_shadow |= CDNC_I2C_CR_DIV_A(best_div_a) |
223 CDNC_I2C_CR_DIV_B(best_div_b);
224 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow);
225
226 sc->i2c_clk_real_freq = clk_out;
227
228 return (0);
229 }
230
231 /* Initialize hardware. */
232 static int
cdnc_i2c_init_hw(struct cdnc_i2c_softc * sc)233 cdnc_i2c_init_hw(struct cdnc_i2c_softc *sc)
234 {
235
236 /* Reset config register and clear FIFO. */
237 sc->cfg_reg_shadow = 0;
238 WR2(sc, CDNC_I2C_CR, CDNC_I2C_CR_CLR_FIFO);
239 sc->hold = 0;
240
241 /* Clear and disable all interrupts. */
242 WR2(sc, CDNC_I2C_ISR, CDNC_I2C_ISR_ALL);
243 WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_ALL);
244
245 /* Max out bogus time-out register. */
246 WR1(sc, CDNC_I2C_TIME_OUT, CDNC_I2C_TIME_OUT_MAX);
247
248 /* Set up clock dividers. */
249 return (cdnc_i2c_set_freq(sc));
250 }
251
252 static int
cdnc_i2c_errs(struct cdnc_i2c_softc * sc,uint16_t istat)253 cdnc_i2c_errs(struct cdnc_i2c_softc *sc, uint16_t istat)
254 {
255
256 DPRINTF("%s: istat=0x%x\n", __func__, istat);
257
258 /* XXX: clean up after errors. */
259
260 /* Reset config register and clear FIFO. */
261 sc->cfg_reg_shadow &= CDNC_I2C_CR_DIV_A_MASK | CDNC_I2C_CR_DIV_B_MASK;
262 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow | CDNC_I2C_CR_CLR_FIFO);
263 sc->hold = 0;
264
265 if (istat & CDNC_I2C_ISR_XFER_TMOUT)
266 return (IIC_ETIMEOUT);
267 else if (istat & CDNC_I2C_ISR_RX_UNDF)
268 return (IIC_EUNDERFLOW);
269 else if (istat & (CDNC_I2C_ISR_RX_OVF | CDNC_I2C_ISR_TX_OVF))
270 return (IIC_EOVERFLOW);
271 else if (istat & CDNC_I2C_ISR_XFER_NACK)
272 return (IIC_ENOACK);
273 else if (istat & CDNC_I2C_ISR_ARB_LOST)
274 return (IIC_EBUSERR); /* XXX: ???? */
275 else
276 /* Should not happen */
277 return (IIC_NOERR);
278 }
279
280 static int
cdnc_i2c_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)281 cdnc_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
282 {
283 struct cdnc_i2c_softc *sc = device_get_softc(dev);
284 int error;
285
286 DPRINTF("%s: speed=%d addr=0x%x\n", __func__, speed, addr);
287
288 I2C_SC_LOCK(sc);
289
290 sc->i2c_clock_freq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
291
292 error = cdnc_i2c_init_hw(sc);
293
294 I2C_SC_UNLOCK(sc);
295
296 return (error ? IIC_ENOTSUPP : IIC_NOERR);
297 }
298
299 static void
cdnc_i2c_intr(void * arg)300 cdnc_i2c_intr(void *arg)
301 {
302 struct cdnc_i2c_softc *sc = (struct cdnc_i2c_softc *)arg;
303 uint16_t status;
304
305 I2C_SC_LOCK(sc);
306
307 sc->interrupts++;
308
309 /* Read active interrupts. */
310 status = RD2(sc, CDNC_I2C_ISR) & ~RD2(sc, CDNC_I2C_IMR);
311
312 /* Clear interrupts. */
313 WR2(sc, CDNC_I2C_ISR, status);
314
315 if (status & CDNC_I2C_ISR_XFER_TMOUT)
316 sc->timeout_ints++;
317
318 sc->istat |= status;
319
320 if (status)
321 wakeup(sc);
322
323 I2C_SC_UNLOCK(sc);
324 }
325
326 static int
cdnc_i2c_xfer_rd(struct cdnc_i2c_softc * sc,struct iic_msg * msg)327 cdnc_i2c_xfer_rd(struct cdnc_i2c_softc *sc, struct iic_msg *msg)
328 {
329 int error = IIC_NOERR;
330 uint16_t flags = msg->flags;
331 uint16_t len = msg->len;
332 int idx = 0, nbytes, last, first = 1;
333 uint16_t statr;
334
335 DPRINTF("%s: flags=0x%x len=%d\n", __func__, flags, len);
336
337 #if 0
338 if (sc->hwtype == HWTYPE_CDNS_R1P10 && (flags & IIC_M_NOSTOP))
339 return (IIC_ENOTSUPP);
340 #endif
341
342 I2C_SC_ASSERT_LOCKED(sc);
343
344 /* Program config register. */
345 sc->cfg_reg_shadow &= CDNC_I2C_CR_DIV_A_MASK | CDNC_I2C_CR_DIV_B_MASK;
346 sc->cfg_reg_shadow |= CDNC_I2C_CR_HOLD | CDNC_I2C_CR_ACKEN |
347 CDNC_I2C_CR_NEA | CDNC_I2C_CR_MAST | CDNC_I2C_CR_RNW;
348 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow | CDNC_I2C_CR_CLR_FIFO);
349 sc->hold = 1;
350
351 while (len > 0) {
352 nbytes = MIN(CDNC_I2C_FIFO_SIZE - 2, len);
353 WR1(sc, CDNC_I2C_TRANS_SIZE, nbytes);
354
355 last = nbytes == len && !(flags & IIC_M_NOSTOP);
356 if (last) {
357 /* Clear HOLD bit on last transfer. */
358 sc->cfg_reg_shadow &= ~CDNC_I2C_CR_HOLD;
359 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow);
360 sc->hold = 0;
361 }
362
363 /* Writing slv address for a start or repeated start. */
364 if (first && !(flags & IIC_M_NOSTART))
365 WR2(sc, CDNC_I2C_ADDR, msg->slave >> 1);
366 first = 0;
367
368 /* Enable FIFO interrupts and wait. */
369 if (last)
370 WR2(sc, CDNC_I2C_IER, CDNC_I2C_ISR_XFER_DONE |
371 CDNC_I2C_ISR_ERRS);
372 else
373 WR2(sc, CDNC_I2C_IER, CDNC_I2C_ISR_XFER_DATA |
374 CDNC_I2C_ISR_ERRS);
375
376 error = mtx_sleep(sc, &sc->sc_mtx, 0, "cdi2c", hz);
377
378 /* Disable FIFO interrupts. */
379 WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_XFER_DATA |
380 CDNC_I2C_ISR_XFER_DONE | CDNC_I2C_ISR_ERRS);
381
382 if (error == EWOULDBLOCK)
383 error = cdnc_i2c_errs(sc, CDNC_I2C_ISR_XFER_TMOUT);
384 else if (sc->istat & CDNC_I2C_ISR_ERRS)
385 error = cdnc_i2c_errs(sc, sc->istat);
386 sc->istat = 0;
387
388 if (error != IIC_NOERR)
389 break;
390
391 /* Read nbytes from FIFO. */
392 while (nbytes-- > 0) {
393 statr = RD2(sc, CDNC_I2C_SR);
394 if (!(statr & CDNC_I2C_SR_RX_VALID)) {
395 printf("%s: RX FIFO underflow?\n", __func__);
396 break;
397 }
398 msg->buf[idx++] = RD2(sc, CDNC_I2C_DATA);
399 len--;
400 }
401 }
402
403 return (error);
404 }
405
406 static int
cdnc_i2c_xfer_wr(struct cdnc_i2c_softc * sc,struct iic_msg * msg)407 cdnc_i2c_xfer_wr(struct cdnc_i2c_softc *sc, struct iic_msg *msg)
408 {
409 int error = IIC_NOERR;
410 uint16_t flags = msg->flags;
411 uint16_t len = msg->len;
412 int idx = 0, nbytes, last, first = 1;
413
414 DPRINTF("%s: flags=0x%x len=%d\n", __func__, flags, len);
415
416 I2C_SC_ASSERT_LOCKED(sc);
417
418 /* Program config register. */
419 sc->cfg_reg_shadow &= CDNC_I2C_CR_DIV_A_MASK | CDNC_I2C_CR_DIV_B_MASK;
420 sc->cfg_reg_shadow |= CDNC_I2C_CR_HOLD | CDNC_I2C_CR_ACKEN |
421 CDNC_I2C_CR_NEA | CDNC_I2C_CR_MAST;
422 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow | CDNC_I2C_CR_CLR_FIFO);
423 sc->hold = 1;
424
425 while (len > 0) {
426 /* Put as much data into fifo as you can. */
427 nbytes = MIN(len, CDNC_I2C_FIFO_SIZE -
428 RD1(sc, CDNC_I2C_TRANS_SIZE) - 1);
429 len -= nbytes;
430 while (nbytes-- > 0)
431 WR2(sc, CDNC_I2C_DATA, msg->buf[idx++]);
432
433 last = len == 0 && !(flags & IIC_M_NOSTOP);
434 if (last) {
435 /* Clear HOLD bit on last transfer. */
436 sc->cfg_reg_shadow &= ~CDNC_I2C_CR_HOLD;
437 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow);
438 sc->hold = 0;
439 }
440
441 /* Perform START if this is start or repeated start. */
442 if (first && !(flags & IIC_M_NOSTART))
443 WR2(sc, CDNC_I2C_ADDR, msg->slave >> 1);
444 first = 0;
445
446 /* Enable FIFO interrupts. */
447 WR2(sc, CDNC_I2C_IER, CDNC_I2C_ISR_XFER_DONE |
448 CDNC_I2C_ISR_ERRS);
449
450 /* Wait for end of data transfer. */
451 error = mtx_sleep(sc, &sc->sc_mtx, 0, "cdi2c", hz);
452
453 /* Disable FIFO interrupts. */
454 WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_XFER_DONE |
455 CDNC_I2C_ISR_ERRS);
456
457 if (error == EWOULDBLOCK)
458 error = cdnc_i2c_errs(sc, CDNC_I2C_ISR_XFER_TMOUT);
459 else if (sc->istat & CDNC_I2C_ISR_ERRS)
460 error = cdnc_i2c_errs(sc, sc->istat);
461 sc->istat = 0;
462 if (error)
463 break;
464 }
465
466 return (error);
467 }
468
469 static int
cdnc_i2c_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)470 cdnc_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
471 {
472 struct cdnc_i2c_softc *sc = device_get_softc(dev);
473 int i, error = IIC_NOERR;
474
475 DPRINTF("%s: nmsgs=%d\n", __func__, nmsgs);
476
477 I2C_SC_LOCK(sc);
478
479 for (i = 0; i < nmsgs; i++) {
480 DPRINTF("%s: msg[%d]: hold=%d slv=0x%x flags=0x%x len=%d\n",
481 __func__, i, sc->hold, msgs[i].slave, msgs[i].flags,
482 msgs[i].len);
483
484 if (!sc->hold && (msgs[i].flags & IIC_M_NOSTART))
485 return (IIC_ENOTSUPP);
486
487 if (msgs[i].flags & IIC_M_RD) {
488 error = cdnc_i2c_xfer_rd(sc, &msgs[i]);
489 if (error != IIC_NOERR)
490 break;
491 } else {
492 error = cdnc_i2c_xfer_wr(sc, &msgs[i]);
493 if (error != IIC_NOERR)
494 break;
495 }
496 }
497
498 I2C_SC_UNLOCK(sc);
499
500 return (error);
501 }
502
503 static void
cdnc_i2c_add_sysctls(device_t dev)504 cdnc_i2c_add_sysctls(device_t dev)
505 {
506 struct cdnc_i2c_softc *sc = device_get_softc(dev);
507 struct sysctl_ctx_list *ctx;
508 struct sysctl_oid_list *child;
509
510 ctx = device_get_sysctl_ctx(dev);
511 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
512
513 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "i2c_clk_real_freq", CTLFLAG_RD,
514 &sc->i2c_clk_real_freq, 0, "i2c clock real frequency");
515
516 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_interrupts", CTLFLAG_RD,
517 &sc->interrupts, 0, "interrupt calls");
518 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_timeouts", CTLFLAG_RD,
519 &sc->timeout_ints, 0, "hardware timeout interrupts");
520 }
521
522
523 static int
cdnc_i2c_probe(device_t dev)524 cdnc_i2c_probe(device_t dev)
525 {
526
527 if (!ofw_bus_status_okay(dev))
528 return (ENXIO);
529
530 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
531 return (ENXIO);
532
533 device_set_desc(dev, "Cadence I2C Controller");
534
535 return (BUS_PROBE_DEFAULT);
536 }
537
538
539 static int cdnc_i2c_detach(device_t);
540
541 static int
cdnc_i2c_attach(device_t dev)542 cdnc_i2c_attach(device_t dev)
543 {
544 struct cdnc_i2c_softc *sc;
545 int rid, err;
546 phandle_t node;
547 pcell_t cell;
548 uint64_t freq;
549
550 sc = device_get_softc(dev);
551 sc->dev = dev;
552 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
553
554 I2C_SC_LOCK_INIT(sc);
555
556 /* Get ref-clock and i2c-clock properties. */
557 node = ofw_bus_get_node(dev);
558 if (OF_getprop(node, "ref-clock", &cell, sizeof(cell)) > 0)
559 sc->ref_clock_freq = fdt32_to_cpu(cell);
560 else if (clk_get_by_ofw_index(dev, node, 0, &sc->ref_clk) == 0) {
561 if ((err = clk_enable(sc->ref_clk)) != 0)
562 device_printf(dev, "Cannot enable clock. err=%d\n",
563 err);
564 else if ((err = clk_get_freq(sc->ref_clk, &freq)) != 0)
565 device_printf(dev,
566 "Cannot get clock frequency. err=%d\n", err);
567 else
568 sc->ref_clock_freq = freq;
569 }
570 else {
571 device_printf(dev, "must have ref-clock property\n");
572 return (ENXIO);
573 }
574 if (OF_getprop(node, "clock-frequency", &cell, sizeof(cell)) > 0)
575 sc->i2c_clock_freq = fdt32_to_cpu(cell);
576 else
577 sc->i2c_clock_freq = CDNC_I2C_DEFAULT_I2C_CLOCK;
578
579 /* Get memory resource. */
580 rid = 0;
581 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
582 RF_ACTIVE);
583 if (sc->mem_res == NULL) {
584 device_printf(dev, "could not allocate memory resources.\n");
585 cdnc_i2c_detach(dev);
586 return (ENOMEM);
587 }
588
589 /* Allocate IRQ. */
590 rid = 0;
591 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
592 RF_ACTIVE);
593 if (sc->irq_res == NULL) {
594 device_printf(dev, "could not allocate IRQ resource.\n");
595 cdnc_i2c_detach(dev);
596 return (ENOMEM);
597 }
598
599 /* Activate the interrupt. */
600 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
601 NULL, cdnc_i2c_intr, sc, &sc->intrhandle);
602 if (err) {
603 device_printf(dev, "could not setup IRQ.\n");
604 cdnc_i2c_detach(dev);
605 return (err);
606 }
607
608 /* Configure the device. */
609 err = cdnc_i2c_init_hw(sc);
610 if (err) {
611 cdnc_i2c_detach(dev);
612 return (err);
613 }
614
615 sc->iicbus = device_add_child(dev, "iicbus", -1);
616
617 cdnc_i2c_add_sysctls(dev);
618
619 /* Probe and attach iicbus when interrupts work. */
620 bus_delayed_attach_children(dev);
621 return (0);
622 }
623
624 static int
cdnc_i2c_detach(device_t dev)625 cdnc_i2c_detach(device_t dev)
626 {
627 struct cdnc_i2c_softc *sc = device_get_softc(dev);
628
629 if (device_is_attached(dev))
630 bus_generic_detach(dev);
631
632 if (sc->ref_clk != NULL) {
633 clk_release(sc->ref_clk);
634 sc->ref_clk = NULL;
635 }
636
637 /* Delete iic bus. */
638 if (sc->iicbus)
639 device_delete_child(dev, sc->iicbus);
640
641 /* Disable hardware. */
642 if (sc->mem_res != NULL) {
643 sc->cfg_reg_shadow = 0;
644 WR2(sc, CDNC_I2C_CR, CDNC_I2C_CR_CLR_FIFO);
645
646 /* Clear and disable all interrupts. */
647 WR2(sc, CDNC_I2C_ISR, CDNC_I2C_ISR_ALL);
648 WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_ALL);
649 }
650
651 /* Teardown and release interrupt. */
652 if (sc->irq_res != NULL) {
653 if (sc->intrhandle)
654 bus_teardown_intr(dev, sc->irq_res, sc->intrhandle);
655 bus_release_resource(dev, SYS_RES_IRQ,
656 rman_get_rid(sc->irq_res), sc->irq_res);
657 sc->irq_res = NULL;
658 }
659
660 /* Release memory resource. */
661 if (sc->mem_res != NULL) {
662 bus_release_resource(dev, SYS_RES_MEMORY,
663 rman_get_rid(sc->mem_res), sc->mem_res);
664 sc->mem_res = NULL;
665 }
666
667 I2C_SC_LOCK_DESTROY(sc);
668
669 return (0);
670 }
671
672
673 static phandle_t
cdnc_i2c_get_node(device_t bus,device_t dev)674 cdnc_i2c_get_node(device_t bus, device_t dev)
675 {
676
677 return (ofw_bus_get_node(bus));
678 }
679
680 static device_method_t cdnc_i2c_methods[] = {
681 /* Device interface */
682 DEVMETHOD(device_probe, cdnc_i2c_probe),
683 DEVMETHOD(device_attach, cdnc_i2c_attach),
684 DEVMETHOD(device_detach, cdnc_i2c_detach),
685
686 /* ofw_bus interface */
687 DEVMETHOD(ofw_bus_get_node, cdnc_i2c_get_node),
688
689 /* iicbus methods */
690 DEVMETHOD(iicbus_callback, iicbus_null_callback),
691 DEVMETHOD(iicbus_reset, cdnc_i2c_reset),
692 DEVMETHOD(iicbus_transfer, cdnc_i2c_transfer),
693
694 DEVMETHOD_END
695 };
696
697 static driver_t cdnc_i2c_driver = {
698 "cdnc_i2c",
699 cdnc_i2c_methods,
700 sizeof(struct cdnc_i2c_softc),
701 };
702
703 DRIVER_MODULE(cdnc_i2c, simplebus, cdnc_i2c_driver, NULL, NULL);
704 DRIVER_MODULE(ofw_iicbus, cdnc_i2c, ofw_iicbus_driver, NULL, NULL);
705 MODULE_DEPEND(cdnc_i2c, iicbus, 1, 1, 1);
706 MODULE_DEPEND(cdnc_i2c, ofw_iicbus, 1, 1, 1);
707 SIMPLEBUS_PNP_INFO(compat_data);
708