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Searched refs:CCOp (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td288 def CCOp : Operand<i32>;
389 // Note that these values must be kept in sync with the CCOp::CondCode enum
958 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
962 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
966 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
970 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
993 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
996 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
1017 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
1020 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
[all …]
H A DSparcInstrUAOSA.td29 (ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, IntRegs:$rs2),
32 (ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, simm5Op:$simm5),
H A DSparcInstr64Bit.td291 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
296 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
304 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
309 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
315 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.td405 def CCOpAsmOperand : AsmOperandClass { let Name = "CCOp"; }
406 def CCOp : Operand<i32>, ImmLeaf<i32, [{
496 // Note that these values must be kept in sync with the CCOp::CondCode enum
730 def rr : RR<opc, (outs I64:$sx), (ins CCOp:$cfw, RC:$sy, I64:$sz, I64:$sd),
733 (i32 CCOp:$cfw)))]>;
736 (ins CCOp:$cfw, immOp:$sy, I64:$sz, I64:$sd),
739 (i32 CCOp:$cfw)))]>;
742 (ins CCOp:$cfw, RC:$sy, mimm:$sz, I64:$sd),
745 (i32 CCOp:$cfw)))]>;
748 (ins CCOp:$cfw, immOp:$sy, mimm:$sz, I64:$sd),
[all …]
H A DVEInstrVec.td60 (ins CCOp:$cf, V64:$vz, I32:$vl),
63 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
66 (ins CCOp:$cf, V64:$vz, I32:$vl),
69 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
766 defm v : RVMKlm<opcStr#"$vy", ", $vz", opc, RCM, (ins CCOp:$vy, RC:$vz)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td232 def CCOp : Operand<i32> {
686 def BRCC : InstBR<(outs), (ins BrTarget:$addr, CCOp:$DDDI),
769 def SCC : InstSCC<(outs GPR:$Rs1), (ins CCOp:$DDDI),
777 (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
789 def BRIND_CC : InstRR<0b101, (outs), (ins GPR:$Rs1, CCOp:$DDDI),
797 def BRIND_CCA : InstRR<0b101, (outs), (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
809 def BRR : InstBRR<(outs), (ins i16imm:$imm16, CCOp:$DDDI),
H A DLanaiISelLowering.cpp1378 SDValue CCOp; in combineSelectAndUse() local
1380 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
1392 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal); in combineSelectAndUse()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.td21 def CCOp : PredicateOperand<i32, (ops i32imm), (ops)>;
397 (outs GPR32:$B), (ins GPR32:$C, GPR32:$B2, CCOp:$cc),
402 (outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
406 (outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp186 struct CCOp { struct in __anon944a62760211::VEOperand
204 struct CCOp CC;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp358 bool Negate, Register CCOp,
4920 Register Val, AArch64CC::CondCode &OutCC, bool Negate, Register CCOp, in emitConjunctionRec() argument
4942 if (!CCOp) in emitConjunctionRec()
4947 CCOp = ExtraCmp->getOperand(0).getReg(); in emitConjunctionRec()
4953 if (!CCOp) { in emitConjunctionRec()
5023 emitConjunctionRec(RHS, RHSCC, NegateR, CCOp, Predicate, MIB); in emitConjunctionRec()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2384 const MachineOperand &CCOp = I.getOperand(1); in selectG_SELECT() local
2385 Register CCReg = CCOp.getReg(); in selectG_SELECT()
2396 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp4313 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get(); in ExpandNode() local
4315 if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) { in ExpandNode()
4334 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp, Tmp1.getValueType()); in ExpandNode()
H A DSelectionDAG.cpp5606 unsigned CCOp = Opcode == ISD::SETCC ? 2 : 4; in canCreateUndefOrPoison() local
5607 ISD::CondCode CCCode = cast<CondCodeSDNode>(Op.getOperand(CCOp))->get(); in canCreateUndefOrPoison()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3552 ISD::CondCode CC, SDValue CCOp, in emitConditionalComparison() argument
3590 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp); in emitConditionalComparison()
3670 AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, in emitConjunctionRec() argument
3693 if (!CCOp.getNode()) in emitConjunctionRec()
3696 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, in emitConjunctionRec()
3698 CCOp = ExtraCmp; in emitConjunctionRec()
3704 if (!CCOp) in emitConjunctionRec()
3707 return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL, in emitConjunctionRec()
3768 SDValue CmpR = emitConjunctionRec(DAG, RHS, RHSCC, NegateR, CCOp, Predicate); in emitConjunctionRec()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp815 struct CCOp { struct in __anon6be9c9a00111::ARMOperand
938 struct CCOp CC;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12664 SDValue CCOp; in combineSelectAndUse() local
12666 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
12679 CCOp, TrueVal, FalseVal); in combineSelectAndUse()