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Searched refs:BottomUp (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.cpp240 } else if (PostRASchedDirection == MISched::BottomUp) { in overridePostRASchedPolicy()
H A DRISCVProcessors.td15 defvar BottomUp = [{ MISched::BottomUp }];
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h197 BottomUp, enumerator
H A DMachinePipeliner.h306 enum OrderKind { BottomUp = 0, TopDown = 1 }; enumerator
H A DMachineScheduler.h113 BottomUp, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineScheduler.cpp188 clEnumValN(MISched::BottomUp, "bottomup",
200 clEnumValN(MISched::BottomUp, "bottomup",
1036 D = ScheduleDAGMI::DumpDirection::BottomUp; in enterRegion()
1406 else if (DumpDir == DumpDirection::BottomUp) in dumpSchedule()
3739 } else if (PreRADirection == MISched::BottomUp) { in initPolicy()
4347 } else if (PostRADirection == MISched::BottomUp) { in initPolicy()
4803 PreRADirection != MISched::TopDown && PreRADirection != MISched::BottomUp; in createInstructionShuffler()
4804 bool TopDown = PreRADirection != MISched::BottomUp; in createInstructionShuffler()
H A DVLIWMachineScheduler.cpp965 } else if (PreRADirection == MISched::BottomUp) { in pickNode()
H A DMachinePipeliner.cpp2504 Order = BottomUp; in computeNodeOrder()
2520 Order = BottomUp; in computeNodeOrder()
2531 Order = BottomUp; in computeNodeOrder()
2583 Order = BottomUp; in computeNodeOrder()