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Searched refs:BasePtrReg (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp1091 Register BasePtrReg = in emitPrologue() local
1196 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), BasePtrReg) in emitPrologue()
1219 bool BPSaved = FuncInfo->hasPrologEpilogSGPRSpillEntry(BasePtrReg); in emitPrologue()
1558 Register BasePtrReg = TRI->getBaseRegister(); in determinePrologEpilogSGPRSaves() local
1559 assert(!MFI->hasPrologEpilogSGPRSpillEntry(BasePtrReg) && in determinePrologEpilogSGPRSaves()
1561 getVGPRSpillLaneOrTempRegister(MF, LiveUnits, BasePtrReg); in determinePrologEpilogSGPRSaves()
1707 Register BasePtrReg = RI->getBaseRegister(); in assignCalleeSavedSpillSlots() local
1711 FuncInfo->getScratchSGPRCopyDstReg(BasePtrReg); in assignCalleeSavedSpillSlots()
1727 } else if (CS.getReg() == BasePtrReg && SGPRForBPSaveRestoreCopy) { in assignCalleeSavedSpillSlots()
H A DSIRegisterInfo.cpp658 MCRegister BasePtrReg = getBaseRegister(); in getReservedRegs() local
659 reserveRegisterTuples(Reserved, BasePtrReg); in getReservedRegs()
660 assert(!isSubRegister(ScratchRSrcReg, BasePtrReg)); in getReservedRegs()
H A DAMDGPURegisterBankInfo.cpp1148 Register BasePtrReg = SrcRegs[0]; in applyMappingLoad() local
1150 MRI.setType(BasePtrReg, PtrTy); in applyMappingLoad()