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Searched refs:BaseOpc (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td623 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
631 def 8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
632 def 16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>, OpSize16;
633 def 32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>, OpSize32;
634 def 64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
637 def 8rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag, 1>;
638 def 16rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag, 1>, PD;
639 def 32rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag, 1>;
640 def 64rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag, 1>;
641 def 8rr_NF_ND : BinOpRR_R<BaseOpc, mnemonic, Xi8, 1>, EVEX_NF;
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H A DX86FastISel.cpp2873 unsigned BaseOpc, CondCode; in fastLowerIntrinsicCall() local
2877 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2879 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2881 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2883 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2885 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2887 BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2902 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) && in fastLowerIntrinsicCall()
2906 bool IsDec = BaseOpc == ISD::SUB; in fastLowerIntrinsicCall()
2911 ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, CI->getZExtValue()); in fastLowerIntrinsicCall()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DMatchContext.h86 auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(), in match() local
88 if (BaseOpc != Opc) in match()
H A DLegalizeVectorTypes.cpp1032 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); in ScalarizeVecOp_VECREDUCE_SEQ()
1035 return DAG.getNode(BaseOpc, SDLoc(N), N->getValueType(0), in ScalarizeVecOp_CMP()
7180 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); in WidenVecOp_VECREDUCE()
7181 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE()
7218 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); in WidenVecOp_VECREDUCE_SEQ()
7219 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE_SEQ()
1028 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); ScalarizeVecOp_VECREDUCE_SEQ() local
7176 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); WidenVecOp_VECREDUCE() local
7214 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); WidenVecOp_VECREDUCE_SEQ() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp704 int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm in CreateLoadStoreMulti() local
716 BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm in CreateLoadStoreMulti()
739 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
757 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
759 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
764 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
770 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h508 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
526 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
H A DAMDGPUBaseInfo.cpp427 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMTBUFOpcode() argument
428 const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMTBUFOpcode()
457 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMUBUFOpcode() argument
458 const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMUBUFOpcode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3219 unsigned BaseOpc = BO.first.getOpcode(); in LowerUnalignedLoad() local
3220 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0) in LowerUnalignedLoad()
3228 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR) in LowerUnalignedLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp9742 unsigned BaseOpc; in lowerVectorMaskVecReduction()
9756 BaseOpc = ISD::AND; in lowerVectorMaskVecReduction()
9764 BaseOpc = ISD::OR; in lowerVectorMaskVecReduction()
9773 BaseOpc = ISD::XOR; in lowerVectorMaskVecReduction()
9790 return DAG.getNode(BaseOpc, DL, Op.getValueType(), SetCC, Op.getOperand(0));
9838 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Op.getOpcode()); in lowerVECREDUCE()
9846 Vec = DAG.getNode(BaseOpc, DL, VecEVT, Lo, Hi); in lowerVECREDUCE()
9866 SDValue StartV = DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags()); in lowerVECREDUCE()
9867 switch (BaseOpc) { in lowerVECREDUCE()
9740 unsigned BaseOpc; lowerVectorMaskVecReduction() local
9836 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Op.getOpcode()); lowerVECREDUCE() local