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Searched refs:BaseOp2 (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2919 const MachineOperand &BaseOp2 = *BaseOps2.front(); in shouldClusterMemOps() local
2931 if ((BaseOp1.isReg() != BaseOp2.isReg()) || in shouldClusterMemOps()
2932 (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) || in shouldClusterMemOps()
2933 (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex())) in shouldClusterMemOps()
2939 const MachineInstr &SecondLdSt = *BaseOp2.getParent(); in shouldClusterMemOps()
2962 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 && in shouldClusterMemOps()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp1015 const MachineOperand *BaseOp1, *BaseOp2; in hasLoopCarriedMemDep() local
1020 TII->getMemOperandWithOffset(DstMI, BaseOp2, Offset2, Offset2IsScalable, in hasLoopCarriedMemDep()
1022 if (BaseOp1->isIdenticalTo(*BaseOp2) && in hasLoopCarriedMemDep()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4903 const MachineOperand &BaseOp2 = *BaseOps2.front(); in shouldClusterMemOps() local
4905 const MachineInstr &SecondLdSt = *BaseOp2.getParent(); in shouldClusterMemOps()
4906 if (BaseOp1.getType() != BaseOp2.getType()) in shouldClusterMemOps()
4913 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) in shouldClusterMemOps()
4951 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
4957 BaseOp2.getIndex(), Offset2, SecondOpc); in shouldClusterMemOps()