Home
last modified time | relevance | path

Searched refs:BaseOffs (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1790 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1795 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1802 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1805 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1810 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1813 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1817 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1820 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2812 if (BaseOffs != other.BaseOffs) in compare()
2834 return !BaseOffs && !Scale && !(BaseGV && BaseReg); in isTrivial()
2848 return ConstantInt::get(IntPtrTy, BaseOffs); in GetFieldAsValue()
2885 BaseOffs = 0; in SetCombinedField()
2910 if (BaseOffs) { in print()
2911 OS << (NeedPlus ? " + " : "") << BaseOffs; in print()
4241 TestAddrMode.BaseOffs += CI->getSExtValue() * TestAddrMode.Scale; in matchScaledValue()
4289 if (AddrMode.BaseOffs) { in matchScaledValue()
4302 TestAddrMode.BaseOffs -= Offset.getLimitedValue(); in matchScaledValue()
4951 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
[all …]
H A DTargetLoweringBase.cpp1896 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
1908 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1913 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp260 auto *Ptr = GetPointerBaseWithConstantOffset(GEP, AM.BaseOffs, *DL); in visit()
H A DSILoadStoreOptimizer.cpp2190 AM.BaseOffs = Dist; in promoteConstantOffsetToImm()
2215 AM.BaseOffs = OtherOffset - AnchorAddr.Offset; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1500 return AM.BaseOffs == 0 && AM.Scale == 0; in isLegalFlatAddressingMode()
1509 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset( in isLegalFlatAddressingMode()
1510 AM.BaseOffs, AddrSpace, FlatVariant)); in isLegalFlatAddressingMode()
1544 if (!TII->isLegalMUBUFImmOffset(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
1586 if (AM.BaseOffs % 4 != 0) in isLegalAddressingMode()
1600 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1605 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1609 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
1614 if (!isInt<21>(AM.BaseOffs)) in isLegalAddressingMode()
1618 if (!isInt<24>(AM.BaseOffs)) in isLegalAddressingMode()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1117 AM.BaseOffs = CstOff->getSExtValue(); // [reg +/- imm] in canFoldInAddressingMode()
1743 AMNew.BaseOffs = CombinedImm.getSExtValue(); in matchPtrAddImmedChain()
1747 AMOld.BaseOffs = MaybeImmVal->Value.getSExtValue(); in matchPtrAddImmedChain()
1757 MatchInfo.Imm = AMNew.BaseOffs; in matchPtrAddImmedChain()
4716 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
4726 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h346 AM.BaseOffs = BaseOffset;
415 AM.BaseOffs = BaseOffset.getFixed(); in getScalingFactorCost()
H A DTargetLowering.h2792 int64_t BaseOffs = 0; member
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp6079 if (!isInt<12>(AM.BaseOffs) && in isLegalAddressingMode()
6080 !(isShiftedInt<14, 2>(AM.BaseOffs) && Subtarget.hasUAL())) in isLegalAddressingMode()
6089 if (AM.HasBaseReg && AM.BaseOffs) in isLegalAddressingMode()
6095 if (AM.HasBaseReg || AM.BaseOffs) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3682 if (!isAligned(A, AM.BaseOffs)) in isLegalAddressingMode()
3685 if (!isInt<11>(AM.BaseOffs >> Log2(A))) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp2583 AM.BaseOffs = BaseOffset.getFixed(); in getScalingFactorCost()
H A DARMISelLowering.cpp19671 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
19683 if (AM.BaseOffs) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1045 int64_t Offs = AM.BaseOffs; in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp788 if (AM.BaseOffs < 0) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp5176 if (!APInt(64, AM.BaseOffs).isSignedIntN(32)) in isLegalAddressingMode()
5180 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp17038 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode()
17042 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
17054 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
17059 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp4389 AM.BaseOffs = BaseOffset.getFixed(); in getScalingFactorCost()
H A DAArch64ISelLowering.cpp17355 if (AMode.HasBaseReg && AMode.BaseOffs && AMode.Scale) in isLegalAddressingMode()
17384 if (AM.HasBaseReg && !AM.BaseOffs && AM.ScalableOffset && !AM.Scale && in isLegalAddressingMode()
17391 return AM.HasBaseReg && !AM.BaseOffs && !AM.ScalableOffset && in isLegalAddressingMode()
17395 return AM.HasBaseReg && !AM.BaseOffs && !AM.ScalableOffset && !AM.Scale; in isLegalAddressingMode()
17412 return Subtarget->getInstrInfo()->isLegalAddressingMode(NumBytes, AM.BaseOffs, in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1090 if (!isInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
1099 if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1151 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
1159 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
1178 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
2358 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode()
2367 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp6749 AM.BaseOffs = BaseOffset.getFixed(); in getScalingFactorCost()
H A DX86ISelLowering.cpp34082 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) in isLegalAddressingMode()
34099 Subtarget.is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1847 return AM.HasBaseReg && AM.Scale == 0 && !AM.BaseOffs; in isLegalAddressingMode()
1850 if (!isInt<12>(AM.BaseOffs)) in isLegalAddressingMode()