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Searched refs:BaseOffs (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1761 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1766 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1773 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1776 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1781 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1784 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1788 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1791 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp3150 if (BaseOffs != other.BaseOffs) in compare()
3172 return !BaseOffs && !Scale && !(BaseGV && BaseReg); in isTrivial()
3186 return ConstantInt::get(IntPtrTy, BaseOffs); in GetFieldAsValue()
3223 BaseOffs = 0; in SetCombinedField()
3248 if (BaseOffs) { in print()
3249 OS << (NeedPlus ? " + " : "") << BaseOffs; in print()
4577 TestAddrMode.BaseOffs += CI->getSExtValue() * TestAddrMode.Scale; in matchScaledValue()
4625 if (AddrMode.BaseOffs) { in matchScaledValue()
4638 TestAddrMode.BaseOffs -= Offset.getLimitedValue(); in matchScaledValue()
5287 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
[all …]
H A DTargetLoweringBase.cpp1999 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
2011 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
2016 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp257 auto *Ptr = GetPointerBaseWithConstantOffset(GEP, AM.BaseOffs, *DL); in visit()
H A DSILoadStoreOptimizer.cpp2260 AM.BaseOffs = Dist; in promoteConstantOffsetToImm()
2285 AM.BaseOffs = OtherOffset - AnchorAddr.Offset; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1611 return AM.BaseOffs == 0 && AM.Scale == 0; in isLegalFlatAddressingMode()
1620 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset( in isLegalFlatAddressingMode()
1621 AM.BaseOffs, AddrSpace, FlatVariant)); in isLegalFlatAddressingMode()
1655 if (!TII->isLegalMUBUFImmOffset(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
1698 if (AM.BaseOffs % 4 != 0) in isLegalAddressingMode()
1712 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1717 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1721 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
1726 if (!isInt<21>(AM.BaseOffs)) in isLegalAddressingMode()
1730 if (!isInt<24>(AM.BaseOffs)) in isLegalAddressingMode()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1185 AM.BaseOffs = CstOff->getSExtValue(); // [reg +/- imm] in canFoldInAddressingMode()
1811 AMNew.BaseOffs = CombinedImm.getSExtValue(); in matchPtrAddImmedChain()
1815 AMOld.BaseOffs = MaybeImmVal->Value.getSExtValue(); in matchPtrAddImmedChain()
1825 MatchInfo.Imm = AMNew.BaseOffs; in matchPtrAddImmedChain()
4844 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
4854 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h449 AM.BaseOffs = BaseOffset;
513 AM.BaseOffs = BaseOffset.getFixed(); in getScalingFactorCost()
H A DTargetLowering.h2885 int64_t BaseOffs = 0; member
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3716 if (!isAligned(A, AM.BaseOffs)) in isLegalAddressingMode()
3719 if (!isInt<11>(AM.BaseOffs >> Log2(A))) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp8361 if (!isInt<12>(AM.BaseOffs) && in isLegalAddressingMode()
8362 !(isShiftedInt<14, 2>(AM.BaseOffs) && Subtarget.hasUAL())) in isLegalAddressingMode()
8371 if (AM.HasBaseReg && AM.BaseOffs) in isLegalAddressingMode()
8377 if (AM.HasBaseReg || AM.BaseOffs) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp989 int64_t Offs = AM.BaseOffs; in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp2725 AM.BaseOffs = BaseOffset.getFixed(); in getScalingFactorCost()
H A DARMISelLowering.cpp19606 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
19618 if (AM.BaseOffs) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4722 if (!APInt(64, AM.BaseOffs).isSignedIntN(32)) in isLegalAddressingMode()
4726 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp972 if (AM.BaseOffs < 0) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp17942 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode()
17946 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
17958 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
17963 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1171 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
1179 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
1198 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
2440 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode()
2449 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1405 if (!isInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
1414 if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp5919 AM.BaseOffs = BaseOffset.getFixed(); in getScalingFactorCost()
H A DAArch64ISelLowering.cpp17775 if (AMode.HasBaseReg && AMode.BaseOffs && AMode.Scale) in isLegalAddressingMode()
17804 if (AM.HasBaseReg && !AM.BaseOffs && AM.ScalableOffset && !AM.Scale && in isLegalAddressingMode()
17811 return AM.HasBaseReg && !AM.BaseOffs && !AM.ScalableOffset && in isLegalAddressingMode()
17815 return AM.HasBaseReg && !AM.BaseOffs && !AM.ScalableOffset && !AM.Scale; in isLegalAddressingMode()
17832 return Subtarget->getInstrInfo()->isLegalAddressingMode(NumBytes, AM.BaseOffs, in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp7113 AM.BaseOffs = BaseOffset.getFixed(); in getScalingFactorCost()
H A DX86ISelLowering.cpp35410 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) in isLegalAddressingMode()
35427 Subtarget.is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2031 return AM.HasBaseReg && AM.Scale == 0 && !AM.BaseOffs; in isLegalAddressingMode()
2034 if (!isInt<12>(AM.BaseOffs)) in isLegalAddressingMode()