Searched refs:BaseIdx (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | Store.cpp | 501 SVal BaseIdx = ElemR->getIndex(); in getLValueElement() local
503 if (!isa<nonloc::ConcreteInt>(BaseIdx)) in getLValueElement()
507 BaseIdx.castAs<nonloc::ConcreteInt>().getValue(); in getLValueElement()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | StackMaps.cpp | 462 unsigned BaseIdx = GCPtrIndices[P.first]; in parseStatepointOpers() local
464 LLVM_DEBUG(dbgs() << "Base : " << BaseIdx << " Derived : " << DerivedIdx in parseStatepointOpers()
466 (void)parseOperand(MOB + BaseIdx, MOE, Locations, LiveOuts); in parseStatepointOpers()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 5973 SDValue BaseIdx = N->getOperand(1); in PromoteIntRes_EXTRACT_SUBVECTOR() local
5987 uint64_t IdxVal = BaseIdx->getAsZExtVal(); in PromoteIntRes_EXTRACT_SUBVECTOR()
5991 BaseIdx.getValueType())); in PromoteIntRes_EXTRACT_SUBVECTOR()
5994 DAG.getConstant(IdxVal % NElts, dl, BaseIdx.getValueType())); in PromoteIntRes_EXTRACT_SUBVECTOR()
6000 SDValue Ops[] = {GetWidenedVector(InOp0), BaseIdx}; in PromoteIntRes_EXTRACT_SUBVECTOR()
6009 SDValue Ops[] = { GetPromotedInteger(InOp0), BaseIdx }; in PromoteIntRes_EXTRACT_SUBVECTOR()
6036 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), BaseIdx, in PromoteIntRes_EXTRACT_SUBVECTOR()
6037 DAG.getConstant(i, dl, BaseIdx.getValueType())); in PromoteIntRes_EXTRACT_SUBVECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | RewriteStatepointsForGC.cpp | 1544 Value *BaseIdx = Builder.getInt32(FindIndex(LiveVariables, BasePtrs[i])); in CreateGCRelocates() local
1555 GCRelocateDecl, {StatepointToken, BaseIdx, LiveIdx}, in CreateGCRelocates()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 563 unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), Align) - Align; in getAlignedHighSGPRForRC() local
564 MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in getAlignedHighSGPRForRC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 5245 unsigned BaseIdx = Op.getConstantOperandVal(2); in getTargetConstantBitsFromNode() local
5246 UndefSrcElts.insertBits(UndefSubElts, BaseIdx); in getTargetConstantBitsFromNode()
5248 EltSrcBits[BaseIdx + i] = EltSubBits[i]; in getTargetConstantBitsFromNode()
5262 unsigned BaseIdx = BaseOfs / EltSizeInBits; in getTargetConstantBitsFromNode() local
5267 UndefElts = UndefElts.extractBits(NumSubElts, BaseIdx); in getTargetConstantBitsFromNode()
5268 if ((BaseIdx + NumSubElts) != NumSrcElts) in getTargetConstantBitsFromNode()
5269 EltBits.erase(EltBits.begin() + BaseIdx + NumSubElts, EltBits.end()); in getTargetConstantBitsFromNode()
5270 if (BaseIdx != 0) in getTargetConstantBitsFromNode()
5271 EltBits.erase(EltBits.begin(), EltBits.begin() + BaseIdx); in getTargetConstantBitsFromNode()
6558 int BaseIdx = i * NumBytesPerElt; in getFauxShuffleMask() local
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