| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MachineScheduler.cpp | 39 const MachineOperand &Base1 = AArch64InstrInfo::getLdStBaseOp(MI1); in mayOverlapWrite() local
42 if (!Base0.isIdenticalTo(Base1)) in mayOverlapWrite()
|
| /freebsd/contrib/llvm-project/clang/lib/AST/ |
| H A D | ASTStructuralEquivalence.cpp | 1915 for (CXXRecordDecl::base_class_iterator Base1 = D1CXX->bases_begin(), in IsStructurallyEquivalent() local
1918 Base1 != BaseEnd1; ++Base1, ++Base2) { in IsStructurallyEquivalent()
1919 if (!IsStructurallyEquivalent(Context, Base1->getType(), in IsStructurallyEquivalent()
1929 Context.Diag1(Base1->getBeginLoc(), diag::note_odr_base) in IsStructurallyEquivalent()
1930 << Base1->getType() << Base1->getSourceRange(); in IsStructurallyEquivalent()
1936 if (Base1->isVirtual() != Base2->isVirtual()) { in IsStructurallyEquivalent()
1945 Context.Diag1(Base1->getBeginLoc(), diag::note_odr_base) in IsStructurallyEquivalent()
1946 << Base1->isVirtual() << Base1->getSourceRange(); in IsStructurallyEquivalent()
2004 const CXXBaseSpecifier *Base1 = D1CXX->bases_begin(); in IsStructurallyEquivalent() local
2005 Context.Diag1(Base1->getBeginLoc(), diag::note_odr_base) in IsStructurallyEquivalent()
[all …]
|
| H A D | ASTImporter.cpp | 2556 for (const auto &Base1 : FromCXX->bases()) { in ImportDefinition() local
2557 ExpectedType TyOrErr = import(Base1.getType()); in ImportDefinition()
2562 if (Base1.isPackExpansion()) { in ImportDefinition()
2563 if (ExpectedSLoc LocOrErr = import(Base1.getEllipsisLoc())) in ImportDefinition()
2571 ImportDefinitionIfNeeded(Base1.getType()->getAsCXXRecordDecl())) in ImportDefinition()
2574 auto RangeOrErr = import(Base1.getSourceRange()); in ImportDefinition()
2578 auto TSIOrErr = import(Base1.getTypeSourceInfo()); in ImportDefinition()
2585 Base1.isVirtual(), in ImportDefinition()
2586 Base1.isBaseOfClass(), in ImportDefinition()
2587 Base1.getAccessSpecifierAsWritten(), in ImportDefinition()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 3219 auto Base1 = MO1->getValue(); in memOpsHaveSameBasePtr() local
3221 if (!Base1 || !Base2) in memOpsHaveSameBasePtr()
3223 Base1 = getUnderlyingObject(Base1); in memOpsHaveSameBasePtr()
3226 if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2)) in memOpsHaveSameBasePtr()
3229 return Base1 == Base2; in memOpsHaveSameBasePtr()
|
| H A D | RISCVISelLowering.cpp | 17563 auto [Base1, Offset1] = ExtractBaseAndOffset(LSNode1->getOperand(OpNum)); in performMemPairCombine()
17587 if (Base1 != Base2) in performMemPairCombine()
17607 tryMemPairCombine(DAG, LSNode1, LSNode2, Base1, Offset1)) in performMemPairCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 3014 SDValue Base1 = in SplitHvxMemOp() local
3031 SDValue Load1 = DAG.getLoad(SingleTy, dl, Chain, Base1, MOp1); in SplitHvxMemOp()
3041 SDValue Store1 = DAG.getStore(Chain, dl, Vals.second, Base1, MOp1); in SplitHvxMemOp()
3060 DAG.getMaskedLoad(SingleTy, dl, Chain, Base1, Offset, Masks.second, in SplitHvxMemOp()
3073 SDValue MStore1 = DAG.getMaskedStore(Chain, dl, Vals.second, Base1, Offset, in SplitHvxMemOp()
|
| H A D | HexagonISelLowering.cpp | 3256 SDValue Base1 = DAG.getMemBasePlusOffset( in LowerUnalignedLoad() local
3269 SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO); in LowerUnalignedLoad()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 546 const auto *Base1 = MO1->getValue(); in memOpsHaveSameBasePtr() local
548 if (!Base1 || !Base2) in memOpsHaveSameBasePtr()
550 Base1 = getUnderlyingObject(Base1); in memOpsHaveSameBasePtr()
553 if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2)) in memOpsHaveSameBasePtr()
556 return Base1 == Base2; in memOpsHaveSameBasePtr()
|
| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Constants.cpp | 2179 auto *Base1 = getAddrDiscriminator()->stripAndAccumulateConstantOffsets( in isKnownCompatibleWith() local
2186 return Base1 == Base2 && Off1 == Off2; in isKnownCompatibleWith()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2956 const MachineOperand *Base1 = nullptr, *Base2 = nullptr; in shouldClusterMemOps() local
2957 if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1, TRI) || in shouldClusterMemOps()
2962 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 && in shouldClusterMemOps()
|
| H A D | PPCISelLowering.cpp | 14667 SDValue Base1 = Loc, Base2 = BaseLoc; in isConsecutiveLSLoc() local
14669 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG); in isConsecutiveLSLoc()
14671 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes)) in isConsecutiveLSLoc()
|