Searched refs:Base0 (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MachineScheduler.cpp | 38 const MachineOperand &Base0 = AArch64InstrInfo::getLdStBaseOp(MI0); in mayOverlapWrite() local
42 if (!Base0.isIdenticalTo(Base1)) in mayOverlapWrite()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 3013 SDValue Base0 = MemN->getBasePtr(); in SplitHvxMemOp() local
3015 DAG.getMemBasePlusOffset(Base0, TypeSize::getFixed(HwLen), dl); in SplitHvxMemOp()
3030 SDValue Load0 = DAG.getLoad(SingleTy, dl, Chain, Base0, MOp0); in SplitHvxMemOp()
3040 SDValue Store0 = DAG.getStore(Chain, dl, Vals.first, Base0, MOp0); in SplitHvxMemOp()
3056 DAG.getMaskedLoad(SingleTy, dl, Chain, Base0, Offset, Masks.first, in SplitHvxMemOp()
3070 SDValue MStore0 = DAG.getMaskedStore(Chain, dl, Vals.first, Base0, Offset, in SplitHvxMemOp()
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| H A D | HexagonISelLowering.cpp | 3254 SDValue Base0 = in LowerUnalignedLoad() local
3268 SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO); in LowerUnalignedLoad()
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