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Searched refs:BX (Results 1 – 25 of 42) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp695 uint16_t BX = im(2); in evaluate() local
696 RC[BX] = RC[BX].is(0) ? BT::BitValue::One in evaluate()
697 : RC[BX].is(1) ? BT::BitValue::Zero in evaluate()
704 uint16_t BX = im(2); in evaluate() local
707 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero) in evaluate()
708 .fill(W1+(W1-BX), W0, Zero); in evaluate()
709 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1); in evaluate()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp191 {codeview::RegisterId::BX, X86::BX}, in initLLVMToSEHAndCVRegMapping()
783 SUB_SUPER(BL, BX, EBX, RBX, R) in getX86SubSuperRegister()
849 B_SUB_SUPER(BX) in getX86SubSuperRegister()
/freebsd/sys/dev/acpica/
H A Dacpi_quirks404 oem: FADT "INTEL " "440BX "
469 oem: FADT "SONY " "440BX CR"
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td190 def BX : X86Reg<"bx", 3, [BL,BH]>;
238 def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;
563 (add AX, CX, DX, SI, DI, BX, BP, SP, R8W, R9W, R10W,
627 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;
647 (add AX, CX, DX, SI, DI, BX, BP, SP)>;
/freebsd/contrib/libpcap/msdos/
H A Dpkt_rx1.s74 ; BX has client handle (stored in RX_ELEMENT.handle).
H A Dpkt_rx0.asm118 ; BX has client handle (stored in RX_ELEMENT.handle).
/freebsd/sys/i386/i386/
H A Dbpf_jit_machdep.h52 #define BX 3 macro
H A Ddb_disasm.c64 #define BX 11 /* (bx) */ macro
819 /*d7*/ { "xlat", false, BYTE, op1(BX), 0 },
1386 case BX: in db_disasm()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h159 ENTRY(BX) \
189 ENTRY(BX) \
H A DX86Disassembler.cpp2229 baseReg = MCOperand::createReg(X86::BX); in translateRMMemory()
2233 baseReg = MCOperand::createReg(X86::BX); in translateRMMemory()
/freebsd/sys/amd64/amd64/
H A Dbpf_jit_machdep.h77 #define BX 3 macro
H A Ddb_disasm.c77 #define BX 11 /* (bx) */ macro
924 /*d7*/ { "xlat", false, BYTE, op1(BX), 0 },
1621 case BX: in db_disasm()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td444 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
447 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
451 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
452 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedFalkorDetails.td1191 (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
1193 (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
1195 (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
1199 (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
1201 (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedKryoDetails.td1510 (instregex "LDRS(BW|BX|HW|HX|W)ui")>;
1516 (instregex "LDRS(BW|BX|HW|HX|W)ro(W|X)")>;
1522 (instregex "LDRS(BW|BX|HW|HX|W)(post|pre)")>;
1540 (instregex "LDTRS(BW|BX|HW|HX|W)i")>;
H A DAArch64SchedAmpere1.td970 (instregex "LDTRS(BW|BX|HW|HX|W)i")>;
974 (instregex "LDURS(BW|BX|HW|HX|W)i")>;
H A DAArch64SchedAmpere1B.td952 (instregex "LDTRS(BW|BX|HW|HX|W)i")>;
956 (instregex "LDURS(BW|BX|HW|HX|W)i")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSLSHardening.cpp235 BuildMI(Entry, DebugLoc(), TII->get(ARM::BX)) in populateThunk()
H A DARMBaseInstrInfo.h672 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
H A DARMAsmPrinter.cpp1506 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in emitInstruction()
2211 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in emitInstruction()
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc8280xp-lenovo-thinkpad-x13s.dts655 firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcdxkmsuc8280.mbn";
1107 firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcadsp8280.mbn";
1113 firmware-name = "qcom/sc8280xp/LENOVO/21BX/qccdsp8280.mbn";
/freebsd/contrib/llvm-project/lldb/source/Plugins/SymbolFile/NativePDB/
H A DCodeViewRegisterMapping.cpp678 case llvm::codeview::RegisterId::BX: in GetRegisterSize()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td393 string BX = Bx; // Appendix of mask operations.
1872 def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, EEW=1>,
1947 def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, EEW=1>,
2000 def "_M_" # mti.BX : VPseudoUnaryNoMaskGPROut,
2002 def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut,
2012 def "_M_" #mti.BX : VPseudoUnaryNoMaskGPROut,
2014 def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskGPROut,
2025 def "_M_" # mti.BX : VPseudoUnaryNoMaskNoPolicy<VR, VR, constraint>,
2029 def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint>,
2053 def "_M_" # mti.BX
[all...]
H A DRISCVInstrInfoVVLPatterns.td2845 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>;
2847 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>;
2900 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX)
2904 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK")
2910 (!cast<Instruction>("PseudoVFIRST_M_" # mti.BX)
2914 (!cast<Instruction>("PseudoVFIRST_M_" # mti.BX # "_MASK")
/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def63 CV_REGISTER(BX, 12)

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