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Searched refs:BW (Results 1 – 25 of 65) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenExtract.cpp150 unsigned BW = Ty->getPrimitiveSizeInBits(); in INITIALIZE_PASS_DEPENDENCY() local
151 if (BW != 32 && BW != 64) in INITIALIZE_PASS_DEPENDENCY()
163 APInt A = APInt(BW, ~0ULL, true).lshr(SR).shl(SL); in INITIALIZE_PASS_DEPENDENCY()
174 uint32_t U = BW - std::max(SL, SR); in INITIALIZE_PASS_DEPENDENCY()
189 APInt C = APInt::getHighBitsSet(BW, BW-U); in INITIALIZE_PASS_DEPENDENCY()
201 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonBitTracker.cpp287 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate() argument
290 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
292 while (I*BW < Ws) { in evaluate()
293 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
H A DHexagonConstPropagation.cpp1585 unsigned BW = A1.getBitWidth(); in evaluateZEXTi() local
1586 (void)BW; in evaluateZEXTi()
1587 assert(Width >= Bits && BW >= Bits); in evaluateZEXTi()
1618 unsigned BW = A1.getBitWidth(); in evaluateSEXTi() local
1619 assert(Width >= Bits && BW >= Bits); in evaluateSEXTi()
1628 if (BW <= 64 && Bits != 0) { in evaluateSEXTi()
1653 if (Bits < BW) in evaluateSEXTi()
1684 unsigned BW = A1.getBitWidth(); in evaluateCLBi() local
1692 Result = APInt(BW, static_cast<uint64_t>(Count), false); in evaluateCLBi()
1720 unsigned BW = A1.getBitWidth(); in evaluateCTBi() local
[all …]
H A DBitTracker.cpp345 uint16_t BW = getRegBitWidth(RR); in getCell() local
350 return RegisterCell::self(0, BW); in getCell()
357 return RegisterCell::self(0, BW); in getCell()
367 return RegisterCell::top(BW); in getCell()
419 uint16_t BW = A.getBitWidth(); in eIMM() local
420 assert((unsigned)BW == A.getBitWidth() && "BitWidth overflow"); in eIMM()
421 RegisterCell Res(BW); in eIMM()
422 for (uint16_t i = 0; i < BW; ++i) in eIMM()
H A DHexagonExpandCondsets.cpp231 bool isIntReg(RegisterRef RR, unsigned &BW);
1101 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { in isIntReg() argument
1106 BW = 32; in isIntReg()
1110 BW = (RR.Sub != 0) ? 32 : 64; in isIntReg()
H A DHexagonBitSimplify.cpp1341 unsigned BN, BW; in processBlock() local
1342 if (!HBS::getSubregMask(RS, BN, BW, MRI)) in processBlock()
1346 if (!usedBitsEqual(RD, RS) && !HBS::isEqual(DC, 0, SC, BN, BW)) in processBlock()
2161 unsigned BN, BW; in genExtractLow() local
2162 if (!HBS::getSubregMask(RS, BN, BW, MRI)) in genExtractLow()
2164 if (BW < W || !HBS::isEqual(RC, 0, SC, BN, W)) in genExtractLow()
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DIVDescriptors.h308 unsigned BW = Ty->getIntegerBitWidth(); in getSentinelValue() local
311 ? APInt::getSignedMinValue(BW) in getSentinelValue()
312 : APInt::getMinValue(BW)); in getSentinelValue()
315 ? APInt::getSignedMaxValue(BW) in getSentinelValue()
316 : APInt::getMaxValue(BW)); in getSentinelValue()
H A DValueLattice.h282 ConstantRange asConstantRange(unsigned BW, bool UndefAllowed = false) const {
288 return ConstantRange::getEmpty(BW);
289 return ConstantRange::getFull(BW);
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DHashRecognize.cpp470 unsigned BW = GenPoly.getBitWidth(); in genSarwateTable() local
472 Table[0] = APInt::getZero(BW); in genSarwateTable()
475 APInt CRCInit = APInt::getSignedMinValue(BW); in genSarwateTable()
478 (CRCInit.isSignBitSet() ? GenPoly : APInt::getZero(BW)); in genSarwateTable()
485 APInt CRCInit(BW, 1); in genSarwateTable()
487 CRCInit = CRCInit.lshr(1) ^ (CRCInit[0] ? GenPoly : APInt::getZero(BW)); in genSarwateTable()
H A DBasicAliasAnalysis.cpp1266 unsigned BW = DecompGEP1.Offset.getBitWidth(); in aliasGEP() local
1268 !isUIntN(BW, V1Size.getValue()) || !isUIntN(BW, V2Size.getValue())) in aliasGEP()
1323 ConstantRange(APInt(BW, 0), APInt(BW, V1Size.getValue()))); in aliasGEP()
1325 ConstantRange(APInt(BW, 0), APInt(BW, V2Size.getValue())); in aliasGEP()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp445 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in generateCondForPow() local
447 if (BW == 8) in generateCondForPow()
449 else if (BW == 16) in generateCondForPow()
451 else if (BW == 32) in generateCondForPow()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DConstantRange.cpp99 uint32_t BW = getBitWidth(); in splitPosNeg() local
100 APInt Zero = APInt::getZero(BW), One = APInt(BW, 1); in splitPosNeg()
101 APInt SignedMin = APInt::getSignedMinValue(BW); in splitPosNeg()
104 BW == 1 ? getEmpty() : ConstantRange(One, SignedMin); in splitPosNeg()
809 auto BW = getBitWidth(); in castOp() local
810 APInt Min = APInt::getMinValue(BW); in castOp()
811 APInt Max = APInt::getMaxValue(BW); in castOp()
812 if (ResultBitWidth > BW) { in castOp()
820 auto BW = getBitWidth(); in castOp() local
821 APInt SMin = APInt::getSignedMinValue(BW); in castOp()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DAggressiveInstCombine.cpp905 unsigned BW = DL.getIndexTypeSizeInBits(PtrOp->getType()); in getStrideAndModOffsetOfGEP() local
907 APInt ModOffset(BW, 0); in getStrideAndModOffsetOfGEP()
912 if (!GEP->collectOffset(DL, BW, VarOffsets, ModOffset)) in getStrideAndModOffsetOfGEP()
932 return {APInt(BW, 1), APInt(BW, 0)}; in getStrideAndModOffsetOfGEP()
964 unsigned BW = DL.getIndexTypeSizeInBits(PtrOp->getType()); in foldPatternedLoads() local
972 ConstOffset = APInt(BW, 0); in foldPatternedLoads()
973 Stride = APInt(BW, LA.value()); in foldPatternedLoads()
/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DBitVector.h807 BitWord BW = Bits[i]; in applyMask() local
812 if (AddBits) BW |= BitWord(M) << b; in applyMask()
813 else BW &= ~(BitWord(M) << b); in applyMask()
815 Bits[i] = BW; in applyMask()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DFloat2Int.cpp169 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in walkBackwards() local
170 auto Input = ConstantRange::getFull(BW); in walkBackwards()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupVectorConstants.cpp697 auto ConvertToBroadcast = [&](unsigned OpSrc, int BW) { in processInstruction() argument
700 llvm::lookupBroadcastFoldTableBySize(OpSrc, BW)) { in processInstruction()
703 FixupEntry Fixups[] = {{(int)OpBcst, 1, BW, rebuildSplatCst}}; in processInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineNegator.cpp265 unsigned BW = X->getType()->getScalarSizeInBits(); in visitImpl() local
266 Constant *BWMinusOne = ConstantInt::get(X->getType(), BW - 1); in visitImpl()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1392 unsigned BW = VT.getScalarSizeInBits(); in ExpandSEXTINREG() local
1394 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT); in ExpandSEXTINREG()
1853 unsigned BW = SrcVT.getScalarSizeInBits(); in ExpandUINT_TO_FLOAT() local
1854 assert((BW == 64 || BW == 32) && in ExpandUINT_TO_FLOAT()
1861 EVT FPVT = BW == 32 ? MVT::f32 : MVT::f64; in ExpandUINT_TO_FLOAT()
1882 SDValue HalfWord = DAG.getConstant(BW / 2, DL, SrcVT); in ExpandUINT_TO_FLOAT()
1887 uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF; in ExpandUINT_TO_FLOAT()
1891 SDValue TWOHW = DAG.getConstantFP(1ULL << (BW / 2), DL, DstVT); in ExpandUINT_TO_FLOAT()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.cpp543 unsigned BW = getScalarOrVectorBitWidth(SpvType); in getOrCreateConstVector() local
544 return getOrCreateCompositeOrNull(ConstVal, I, SpvType, TII, ConstVec, BW, in getOrCreateConstVector()
562 unsigned BW = getScalarOrVectorBitWidth(SpvType); in getOrCreateConstVector() local
563 return getOrCreateCompositeOrNull(ConstVal, I, SpvType, TII, ConstVec, BW, in getOrCreateConstVector()
577 unsigned BW = getScalarOrVectorBitWidth(SpvBaseTy); in getOrCreateConstIntArray() local
589 return getOrCreateCompositeOrNull(CI, I, SpvType, TII, UniqueKey, BW, in getOrCreateConstIntArray()
642 unsigned BW = getScalarOrVectorBitWidth(SpvType); in getOrCreateConsIntVector() local
644 ConstVec, BW, in getOrCreateConsIntVector()
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DDeclObjC.h1960 TypeSourceInfo *TInfo, AccessControl ac, Expr *BW, in ObjCIvarDecl() argument
1962 : FieldDecl(ObjCIvar, DC, StartLoc, IdLoc, Id, T, TInfo, BW, in ObjCIvarDecl()
1971 Expr *BW = nullptr, bool synthesized = false);
2030 QualType T, Expr *BW) in ObjCAtDefsFieldDecl() argument
2033 BW, /*Mutable=*/false, /*HasInit=*/ICIS_NoInit) {} in ObjCAtDefsFieldDecl()
2041 QualType T, Expr *BW);
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td444 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
447 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
451 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
452 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedFalkorDetails.td1191 (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
1193 (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
1195 (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
1199 (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
1201 (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DDeclObjC.cpp1835 Expr *BW, bool synthesized) { in Create() argument
1862 return new (C, DC) ObjCIvarDecl(DC, StartLoc, IdLoc, Id, T, TInfo, ac, BW, in Create()
1910 IdentifierInfo *Id, QualType T, Expr *BW) { in Create() argument
1911 return new (C, DC) ObjCAtDefsFieldDecl(DC, StartLoc, IdLoc, Id, T, BW); in Create()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp405 unsigned BW = DL.getIndexTypeSizeInBits(GEP->getType()); in GEPToVectorIndex() local
407 APInt ConstOffset(BW, 0); in GEPToVectorIndex()
428 if (!CurGEP->collectOffset(DL, BW, VarOffsets, ConstOffset)) in GEPToVectorIndex()
/freebsd/contrib/libdivsufsort/include/
H A Ddivsufsort.h.cmake115 * Inverse BW-transforms a given BWTed string.

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