| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 68 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in BPFTargetLowering()
136 setOperationAction(ISD::BR_CC, MVT::i32, in BPFTargetLowering()
317 case ISD::BR_CC: in LowerOperation()
702 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, in LowerBR_CC()
793 case BPFISD::BR_CC: in getTargetNodeName()
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| H A D | BPFISelLowering.h | 29 BR_CC, enumerator
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| H A D | BPFInstrInfo.td | 44 def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1187 BR_CC, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 88 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in MSP430TargetLowering()
89 setOperationAction(ISD::BR_CC, MVT::i16, Custom); in MSP430TargetLowering()
228 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation()
1017 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), in LowerBR_CC()
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| H A D | MSP430InstrInfo.td | 63 def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 112 setOperationAction(ISD::BR_CC, MVT::i32, Legal); in XtensaTargetLowering()
113 setOperationAction(ISD::BR_CC, MVT::i64, Expand); in XtensaTargetLowering()
120 setOperationAction(ISD::BR_CC, MVT::f32, Legal); in XtensaTargetLowering()
123 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in XtensaTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 147 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in ARCTargetLowering()
778 case ISD::BR_CC: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 83 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in LanaiTargetLowering()
171 case ISD::BR_CC: in LowerOperation()
869 return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest, in LowerBR_CC()
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| H A D | LanaiInstrInfo.td | 52 def LanaiBrCC : SDNode<"LanaiISD::BR_CC", SDT_LanaiBrCC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 102 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in AVRTargetLowering()
103 setOperationAction(ISD::BR_CC, MVT::i16, Custom); in AVRTargetLowering()
104 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in AVRTargetLowering()
105 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in AVRTargetLowering()
936 case ISD::BR_CC: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1073 case ISD::BR_CC: { in LegalizeOp()
1081 unsigned CompareOperand = Opc == ISD::BR_CC ? 2 in LegalizeOp()
4212 TLI.isOperationLegalOrCustom(ISD::BR_CC, in ExpandNode()
4214 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, Tmp2.getOperand(2), in ExpandNode()
4225 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, in ExpandNode()
4381 case ISD::BR_CC: { in ExpandNode()
4400 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, in ExpandNode()
4405 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, in ExpandNode()
5314 if (Node->getOpcode() == ISD::BR_CC || in PromoteNode()
5625 case ISD::BR_CC: { in PromoteNode()
[all …]
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| H A D | SelectionDAGDumper.cpp | 442 case ISD::BR_CC: return "br_cc"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 1141 case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break; in SoftenFloatOperand()
2291 case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break; in ExpandFloatOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1717 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in SparcTargetLowering()
1718 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in SparcTargetLowering()
1719 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in SparcTargetLowering()
1720 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in SparcTargetLowering()
1744 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in SparcTargetLowering()
3121 case ISD::BR_CC: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 70 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in CSKYTargetLowering()
130 setOperationAction(ISD::BR_CC, VT, Expand); in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1697 setOperationAction(ISD::BR_CC, VT, Expand); in HexagonTargetLowering()
1701 setOperationAction(ISD::BR_CC, VT, Expand); in HexagonTargetLowering()
1704 setOperationAction(ISD::BR_CC, MVT::Other, Expand); in HexagonTargetLowering()
1730 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 423 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in MipsTargetLowering()
424 setOperationAction(ISD::BR_CC, MVT::f64, Expand); in MipsTargetLowering()
425 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in MipsTargetLowering()
426 setOperationAction(ISD::BR_CC, MVT::i64, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 62 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in XCoreTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 98 setOperationAction(ISD::BR_CC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 296 setOperationAction(ISD::BR_CC, XLenVT, Expand); in RISCVTargetLowering()
490 setOperationAction(ISD::BR_CC, MVT::bf16, Expand); in RISCVTargetLowering()
531 setOperationAction(ISD::BR_CC, MVT::f16, Expand); in RISCVTargetLowering()
562 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in RISCVTargetLowering()
618 setOperationAction(ISD::BR_CC, MVT::f64, Expand); in RISCVTargetLowering()
9342 return DAG.getNode(RISCVISD::BR_CC, DL, Op.getValueType(), Op.getOperand(0), in lowerBRCOND()
9346 return DAG.getNode(RISCVISD::BR_CC, DL, Op.getValueType(), Op.getOperand(0), in lowerBRCOND()
18336 if (Opcode != RISCVISD::SELECT_CC && Opcode != RISCVISD::BR_CC) in combine_CC()
20062 case RISCVISD::BR_CC: { in PerformDAGCombine()
20069 return DAG.getNode(RISCVISD::BR_CC, DL, N->getValueType(0), in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 821 setTargetDAGCombine({ISD::BRCOND, ISD::BR_CC}); in ARMTargetLowering()
1407 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in ARMTargetLowering()
1409 setOperationAction(ISD::BR_CC, MVT::f16, Custom); in ARMTargetLowering()
1410 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in ARMTargetLowering()
1411 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in ARMTargetLowering()
10640 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation()
18325 assert(N->getOpcode() == ISD::BR_CC && "Expected BRCOND or BR_CC!"); in PerformHWLoopCombine()
18968 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget); in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 503 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in AArch64TargetLowering()
504 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in AArch64TargetLowering()
505 setOperationAction(ISD::BR_CC, MVT::f16, Custom); in AArch64TargetLowering()
506 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in AArch64TargetLowering()
507 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in AArch64TargetLowering()
569 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in AArch64TargetLowering()
790 ISD::BR_CC, in AArch64TargetLowering()
860 setOperationAction(ISD::BR_CC, V4Narrow, Expand); in AArch64TargetLowering()
886 setOperationAction(ISD::BR_CC, V8Narrow, Expand); in AArch64TargetLowering()
1234 ISD::BR_CC, ISD::FADD, ISD::FSUB, in AArch64TargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 128 setOperationAction(ISD::BR_CC, GRLenVT, Expand); in LoongArchTargetLowering()
192 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in LoongArchTargetLowering()
239 setOperationAction(ISD::BR_CC, MVT::f64, Expand); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2898 case ISD::BR_CC: in isI32Insn()
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