| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 67 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in BPFTargetLowering()
128 setOperationAction(ISD::BR_CC, MVT::i32, in BPFTargetLowering()
306 case ISD::BR_CC: in LowerOperation()
653 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, in LowerBR_CC()
685 case BPFISD::BR_CC: in getTargetNodeName()
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| H A D | BPFISelLowering.h | 29 BR_CC, enumerator
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| H A D | BPFInstrInfo.td | 44 def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.h | 49 // BR_CC - Used to glue together a conditional branch and comparison
50 BR_CC, enumerator
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| H A D | LanaiISelLowering.cpp | 85 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in LanaiTargetLowering()
178 case ISD::BR_CC: in LowerOperation()
881 return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest, in LowerBR_CC()
1111 case LanaiISD::BR_CC: in getTargetNodeName()
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| H A D | LanaiInstrInfo.td | 52 def LanaiBrCC : SDNode<"LanaiISD::BR_CC", SDT_LanaiBrCC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.h | 60 BR_CC, enumerator
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| H A D | MSP430ISelLowering.cpp | 89 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in MSP430TargetLowering()
90 setOperationAction(ISD::BR_CC, MVT::i16, Custom); in MSP430TargetLowering()
349 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation()
1139 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), in LowerBR_CC()
1377 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC"; in getTargetNodeName()
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| H A D | MSP430InstrInfo.td | 63 def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 88 setOperationAction(ISD::BR_CC, MVT::i32, Legal); in XtensaTargetLowering()
89 setOperationAction(ISD::BR_CC, MVT::i64, Expand); in XtensaTargetLowering()
90 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in XtensaTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1118 BR_CC, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 146 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in ARCTargetLowering()
794 case ISD::BR_CC: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 103 setOperationAction(ISD::BR_CC, MVT::i8, Custom); in AVRTargetLowering()
104 setOperationAction(ISD::BR_CC, MVT::i16, Custom); in AVRTargetLowering()
105 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in AVRTargetLowering()
106 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in AVRTargetLowering()
992 case ISD::BR_CC: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1043 case ISD::BR_CC: { in LegalizeOp()
1051 unsigned CompareOperand = Opc == ISD::BR_CC ? 2 in LegalizeOp()
4074 TLI.isOperationLegalOrCustom(ISD::BR_CC, in ExpandNode()
4076 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, Tmp2.getOperand(2), in ExpandNode()
4087 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, in ExpandNode()
4243 case ISD::BR_CC: { in ExpandNode()
4262 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, in ExpandNode()
4267 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, in ExpandNode()
5107 if (Node->getOpcode() == ISD::BR_CC || in PromoteNode()
5415 case ISD::BR_CC: { in PromoteNode()
[all …]
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| H A D | SelectionDAGDumper.cpp | 422 case ISD::BR_CC: return "br_cc"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 999 case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break; in SoftenFloatOperand()
2075 case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break; in ExpandFloatOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1724 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in SparcTargetLowering()
1725 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in SparcTargetLowering()
1726 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in SparcTargetLowering()
1727 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in SparcTargetLowering()
1748 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in SparcTargetLowering()
3261 case ISD::BR_CC: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 70 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in CSKYTargetLowering()
130 setOperationAction(ISD::BR_CC, VT, Expand); in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 44 BR_CC, enumerator
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| H A D | RISCVISelLowering.cpp | 245 setOperationAction(ISD::BR_CC, XLenVT, Expand); in RISCVTargetLowering()
247 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in RISCVTargetLowering()
472 setOperationAction(ISD::BR_CC, MVT::bf16, Expand); in RISCVTargetLowering()
501 setOperationAction(ISD::BR_CC, MVT::f16, Expand); in RISCVTargetLowering()
534 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in RISCVTargetLowering()
580 setOperationAction(ISD::BR_CC, MVT::f64, Expand); in RISCVTargetLowering()
7885 return DAG.getNode(RISCVISD::BR_CC, DL, Op.getValueType(), Op.getOperand(0), in lowerBRCOND()
7889 return DAG.getNode(RISCVISD::BR_CC, DL, Op.getValueType(), Op.getOperand(0), in lowerBRCOND()
15774 // Perform common combines for BR_CC and SELECT_CC condtions. in combine_CC()
17018 case RISCVISD::BR_CC in PerformDAGCombine()
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1627 // Expand BR_CC and SELECT_CC for all integer and fp types. in HexagonTargetLowering()
1629 setOperationAction(ISD::BR_CC, VT, Expand); in HexagonTargetLowering()
1633 setOperationAction(ISD::BR_CC, VT, Expand); in HexagonTargetLowering()
1636 setOperationAction(ISD::BR_CC, MVT::Other, Expand); in HexagonTargetLowering()
1660 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 415 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in MipsTargetLowering()
416 setOperationAction(ISD::BR_CC, MVT::f64, Expand); in MipsTargetLowering()
417 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in MipsTargetLowering()
418 setOperationAction(ISD::BR_CC, MVT::i64, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 113 setOperationAction(ISD::BR_CC, GRLenVT, Expand); in LoongArchTargetLowering()
171 setOperationAction(ISD::BR_CC, MVT::f32, Expand); in LoongArchTargetLowering()
208 setOperationAction(ISD::BR_CC, MVT::f64, Expand); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 90 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in XCoreTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 99 setOperationAction(ISD::BR_CC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
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